From: Dave Hansen <dave.hansen@linux.intel.com>
Today, the only code that cares about the platform ID is the microcode
update code itself. To facilitate storing the platform ID in a more
generic place and using it outside of the microcode update itself, put
the enumeration into a helper function. Mirror
intel_get_microcode_revision()'s naming and location.
But, moving away from intel_collect_cpu_info() means that the model
and family information in CPUID is not readily available. Just call
CPUID again.
Note that the microcode header is a mask of supported platform IDs.
Only stick the ID part in the helper. Leave the 1<<id part in the
microcode handling.
Also note that the PII is weird. It does not really have a platform
ID because it doesn't even have the MSR. Just consider it to be
platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
real oddball here being the only CPU with Linux microcode updates
but no platform ID. It's worth calling it out by name.
This does subtly change the sig->pf for the PII though from 0x0
to 0x1. Make up for that by ignoring sig->pf when the microcode
update platform mask is 0x0.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Cc: Thomas Gleixner <tglx@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
Cc: x86@kernel.org
Cc: Jon Kohler <jon@nutanix.com>
--
Changes from v3:
* Handle the empty platform mask on the PII
---
b/arch/x86/kernel/cpu/microcode/intel.c | 53 +++++++++++++++++++++++++-------
1 file changed, 42 insertions(+), 11 deletions(-)
diff -puN arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags arch/x86/kernel/cpu/microcode/intel.c
--- a/arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags 2026-03-04 09:19:02.438748485 -0800
+++ b/arch/x86/kernel/cpu/microcode/intel.c 2026-03-04 09:19:02.441748599 -0800
@@ -120,19 +120,43 @@ static inline unsigned int exttable_size
return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
}
+/*
+ * Use CPUID to generate a "vfm" value. Useful
+ * before 'cpuinfo_x86' structures are populated.
+ */
+static u32 intel_cpuid_vfm(void)
+{
+ u32 eax = cpuid_eax(1);
+ u32 fam = x86_family(eax);
+ u32 model = x86_model(eax);
+
+ return IFM(fam, model);
+}
+
+static u32 intel_get_platform_id(void)
+{
+ unsigned int val[2];
+
+ /*
+ * This can be called early. Use CPUID directly instead of
+ * relying on cpuinfo_x86 which may not be fully initialized.
+ * The PII does not have MSR_IA32_PLATFORM_ID. Everything
+ * before _it_ has no microcode (for Linux at least).
+ */
+ if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH)
+ return 0;
+
+ /* get processor flags from MSR 0x17 */
+ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+
+ return (val[1] >> 18) & 7;
+}
+
void intel_collect_cpu_info(struct cpu_signature *sig)
{
sig->sig = cpuid_eax(1);
- sig->pf = 0;
sig->rev = intel_get_microcode_revision();
-
- if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) {
- unsigned int val[2];
-
- /* get processor flags from MSR 0x17 */
- native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
- sig->pf = 1 << ((val[1] >> 18) & 7);
- }
+ sig->pf = 1 << intel_get_platform_id();
}
EXPORT_SYMBOL_GPL(intel_collect_cpu_info);
@@ -142,8 +166,15 @@ static inline bool cpu_signatures_match(
if (s1->sig != sig2)
return false;
- /* Processor flags are either both 0 or they intersect. */
- return ((!s1->pf && !pf2) || (s1->pf & pf2));
+ /*
+ * Consider an empty mask to match everything. This
+ * should only occur for one CPU model, the PII.
+ */
+ if (!pf2)
+ return true;
+
+ /* Is the CPU's platform ID in the signature mask? */
+ return s1->pf & pf2;
}
bool intel_find_matching_signature(void *mc, struct cpu_signature *sig)
_On Wed, Mar 04, 2026 at 10:10:18AM -0800, Dave Hansen wrote:
>
> From: Dave Hansen <dave.hansen@linux.intel.com>
>
> Today, the only code that cares about the platform ID is the microcode
> update code itself. To facilitate storing the platform ID in a more
> generic place and using it outside of the microcode update itself, put
> the enumeration into a helper function. Mirror
> intel_get_microcode_revision()'s naming and location.
>
> But, moving away from intel_collect_cpu_info() means that the model
> and family information in CPUID is not readily available. Just call
> CPUID again.
Not a big deal after Ahmed's set lands.
> Note that the microcode header is a mask of supported platform IDs.
> Only stick the ID part in the helper. Leave the 1<<id part in the
> microcode handling.
>
> Also note that the PII is weird. It does not really have a platform
> ID because it doesn't even have the MSR. Just consider it to be
> platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
> real oddball here being the only CPU with Linux microcode updates
> but no platform ID. It's worth calling it out by name.
>
> This does subtly change the sig->pf for the PII though from 0x0
> to 0x1. Make up for that by ignoring sig->pf when the microcode
> update platform mask is 0x0.
>
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
> Cc: Thomas Gleixner <tglx@kernel.org>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: "H. Peter Anvin" <hpa@zytor.com>
> Cc: Tony Luck <tony.luck@intel.com>
> Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
> Cc: x86@kernel.org
> Cc: Jon Kohler <jon@nutanix.com>
>
> --
>
> Changes from v3:
> * Handle the empty platform mask on the PII
>
> ---
>
> b/arch/x86/kernel/cpu/microcode/intel.c | 53 +++++++++++++++++++++++++-------
> 1 file changed, 42 insertions(+), 11 deletions(-)
>
> diff -puN arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags arch/x86/kernel/cpu/microcode/intel.c
> --- a/arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags 2026-03-04 09:19:02.438748485 -0800
> +++ b/arch/x86/kernel/cpu/microcode/intel.c 2026-03-04 09:19:02.441748599 -0800
> @@ -120,19 +120,43 @@ static inline unsigned int exttable_size
> return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
> }
>
> +/*
> + * Use CPUID to generate a "vfm" value. Useful
> + * before 'cpuinfo_x86' structures are populated.
> + */
Use the full length of 80-ish cols:
/*
* Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86
* structures are populated.
*/
> +static u32 intel_cpuid_vfm(void)
> +{
> + u32 eax = cpuid_eax(1);
> + u32 fam = x86_family(eax);
> + u32 model = x86_model(eax);
> +
> + return IFM(fam, model);
> +}
That helper looks pretty generic. We should remember to pull it up if we end
up needing it somewhere else...
Otherwise, LGTM.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On Wed, Mar 04, 2026 at 10:10:18AM -0800, Dave Hansen wrote:
>
> From: Dave Hansen <dave.hansen@linux.intel.com>
>
> Today, the only code that cares about the platform ID is the microcode
> update code itself. To facilitate storing the platform ID in a more
> generic place and using it outside of the microcode update itself, put
> the enumeration into a helper function. Mirror
> intel_get_microcode_revision()'s naming and location.
>
> But, moving away from intel_collect_cpu_info() means that the model
> and family information in CPUID is not readily available. Just call
> CPUID again.
>
> Note that the microcode header is a mask of supported platform IDs.
> Only stick the ID part in the helper. Leave the 1<<id part in the
> microcode handling.
>
> Also note that the PII is weird. It does not really have a platform
> ID because it doesn't even have the MSR. Just consider it to be
> platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
^
I think you meant PIII here?
> real oddball here being the only CPU with Linux microcode updates
> but no platform ID. It's worth calling it out by name.
>
> This does subtly change the sig->pf for the PII though from 0x0
> to 0x1. Make up for that by ignoring sig->pf when the microcode
> update platform mask is 0x0.
>
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
> Cc: Thomas Gleixner <tglx@kernel.org>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: "H. Peter Anvin" <hpa@zytor.com>
> Cc: Tony Luck <tony.luck@intel.com>
> Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
> Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
> Cc: x86@kernel.org
> Cc: Jon Kohler <jon@nutanix.com>
>
> --
>
> Changes from v3:
> * Handle the empty platform mask on the PII
>
> ---
>
> b/arch/x86/kernel/cpu/microcode/intel.c | 53 +++++++++++++++++++++++++-------
> 1 file changed, 42 insertions(+), 11 deletions(-)
>
> diff -puN arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags arch/x86/kernel/cpu/microcode/intel.c
> --- a/arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags 2026-03-04 09:19:02.438748485 -0800
> +++ b/arch/x86/kernel/cpu/microcode/intel.c 2026-03-04 09:19:02.441748599 -0800
> @@ -120,19 +120,43 @@ static inline unsigned int exttable_size
> return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
> }
>
> +/*
> + * Use CPUID to generate a "vfm" value. Useful
> + * before 'cpuinfo_x86' structures are populated.
> + */
> +static u32 intel_cpuid_vfm(void)
> +{
> + u32 eax = cpuid_eax(1);
> + u32 fam = x86_family(eax);
> + u32 model = x86_model(eax);
Nit, is s/eax/sig/ more clear?
u32 sig = cpuid_eax(1);
u32 fam = x86_family(sig);
u32 model = x86_model(sig);
Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
On 3/4/26 17:38, Pawan Gupta wrote:
>> +/*
>> + * Use CPUID to generate a "vfm" value. Useful
>> + * before 'cpuinfo_x86' structures are populated.
>> + */
>> +static u32 intel_cpuid_vfm(void)
>> +{
>> + u32 eax = cpuid_eax(1);
>> + u32 fam = x86_family(eax);
>> + u32 model = x86_model(eax);
> Nit, is s/eax/sig/ more clear?
>
> u32 sig = cpuid_eax(1);
> u32 fam = x86_family(sig);
> u32 model = x86_model(sig);
It's debatable. It's nice having the 'sig' explain what's in EAX. But
'sig' is pretty generic and the code is all right here anyway. I think
I'll leave it as 'eax'.
On 3/4/2026 5:38 PM, Pawan Gupta wrote:
> On Wed, Mar 04, 2026 at 10:10:18AM -0800, Dave Hansen wrote:
>> Also note that the PII is weird. It does not really have a platform
>> ID because it doesn't even have the MSR. Just consider it to be
>> platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
> ^
> I think you meant PIII here?
>
What Dave has here is correct. You can blame me for the confusion.
Family 6, model 5 is DESCHUTES but Pentium II and not III.
I incorrectly named it INTEL_PENTIUM_III_DESCHUTES in commit
7e6b0a2e4152 ("x86/microcode: Update the Intel processor flag scan
check"). It should have been named INTEL_PENTIUM_II_DESCHUTES.
Anyway, there are no other users of this. So after this series merges
I'll send a cleanup patch deleting the #define completely.
>> real oddball here being the only CPU with Linux microcode updates
>> but no platform ID. It's worth calling it out by name.
>>
On Wed, Mar 04, 2026 at 10:28:13PM -0800, Sohil Mehta wrote:
> On 3/4/2026 5:38 PM, Pawan Gupta wrote:
> > On Wed, Mar 04, 2026 at 10:10:18AM -0800, Dave Hansen wrote:
>
> >> Also note that the PII is weird. It does not really have a platform
> >> ID because it doesn't even have the MSR. Just consider it to be
> >> platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
> > ^
> > I think you meant PIII here?
> >
>
> What Dave has here is correct. You can blame me for the confusion.
> Family 6, model 5 is DESCHUTES but Pentium II and not III.
>
> I incorrectly named it INTEL_PENTIUM_III_DESCHUTES in commit
> 7e6b0a2e4152 ("x86/microcode: Update the Intel processor flag scan
> check"). It should have been named INTEL_PENTIUM_II_DESCHUTES.
>
> Anyway, there are no other users of this. So after this series merges
> I'll send a cleanup patch deleting the #define completely.
Ohk, thanks for the clarification.
The following commit has been merged into the x86/microcode branch of tip:
Commit-ID: 238be4ba87605da69de2131e8736be7a0d299e00
Gitweb: https://git.kernel.org/tip/238be4ba87605da69de2131e8736be7a0d299e00
Author: Dave Hansen <dave.hansen@linux.intel.com>
AuthorDate: Wed, 04 Mar 2026 10:10:18 -08:00
Committer: Dave Hansen <dave.hansen@linux.intel.com>
CommitterDate: Thu, 05 Mar 2026 12:25:18 -08:00
x86/microcode: Refactor platform ID enumeration into a helper
Today, the only code that cares about the platform ID is the microcode
update code itself. To facilitate storing the platform ID in a more
generic place and using it outside of the microcode update itself, put
the enumeration into a helper function. Mirror
intel_get_microcode_revision()'s naming and location.
But, moving away from intel_collect_cpu_info() means that the model
and family information in CPUID is not readily available. Just call
CPUID again.
Note that the microcode header is a mask of supported platform IDs.
Only stick the ID part in the helper. Leave the 1<<id part in the
microcode handling.
Also note that the PII is weird. It does not really have a platform
ID because it doesn't even have the MSR. Just consider it to be
platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
real oddball here being the only CPU with Linux microcode updates
but no platform ID. It's worth calling it out by name.
This does subtly change the sig->pf for the PII though from 0x0
to 0x1. Make up for that by ignoring sig->pf when the microcode
update platform mask is 0x0.
[ dhansen: reflow comment for bpetkov ]
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Link: https://patch.msgid.link/20260304181018.EB6404F8@davehans-spike.ostc.intel.com
---
arch/x86/kernel/cpu/microcode/intel.c | 54 ++++++++++++++++++++------
1 file changed, 43 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 8744f3a..83c6cd2 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -120,19 +120,44 @@ static inline unsigned int exttable_size(struct extended_sigtable *et)
return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
}
+
+/*
+ * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86
+ * structures are populated.
+ */
+static u32 intel_cpuid_vfm(void)
+{
+ u32 eax = cpuid_eax(1);
+ u32 fam = x86_family(eax);
+ u32 model = x86_model(eax);
+
+ return IFM(fam, model);
+}
+
+static u32 intel_get_platform_id(void)
+{
+ unsigned int val[2];
+
+ /*
+ * This can be called early. Use CPUID directly instead of
+ * relying on cpuinfo_x86 which may not be fully initialized.
+ * The PII does not have MSR_IA32_PLATFORM_ID. Everything
+ * before _it_ has no microcode (for Linux at least).
+ */
+ if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH)
+ return 0;
+
+ /* get processor flags from MSR 0x17 */
+ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+
+ return (val[1] >> 18) & 7;
+}
+
void intel_collect_cpu_info(struct cpu_signature *sig)
{
sig->sig = cpuid_eax(1);
- sig->pf = 0;
sig->rev = intel_get_microcode_revision();
-
- if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) {
- unsigned int val[2];
-
- /* get processor flags from MSR 0x17 */
- native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
- sig->pf = 1 << ((val[1] >> 18) & 7);
- }
+ sig->pf = 1 << intel_get_platform_id();
}
EXPORT_SYMBOL_GPL(intel_collect_cpu_info);
@@ -142,8 +167,15 @@ static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int s
if (s1->sig != sig2)
return false;
- /* Processor flags are either both 0 or they intersect. */
- return ((!s1->pf && !pf2) || (s1->pf & pf2));
+ /*
+ * Consider an empty mask to match everything. This
+ * should only occur for one CPU model, the PII.
+ */
+ if (!pf2)
+ return true;
+
+ /* Is the CPU's platform ID in the signature mask? */
+ return s1->pf & pf2;
}
bool intel_find_matching_signature(void *mc, struct cpu_signature *sig)The following commit has been merged into the x86/microcode branch of tip:
Commit-ID: da67a0320397125fcbb2e856a31889150c648f3a
Gitweb: https://git.kernel.org/tip/da67a0320397125fcbb2e856a31889150c648f3a
Author: Dave Hansen <dave.hansen@linux.intel.com>
AuthorDate: Wed, 04 Mar 2026 10:10:18 -08:00
Committer: Dave Hansen <dave.hansen@linux.intel.com>
CommitterDate: Thu, 05 Mar 2026 10:41:10 -08:00
x86/microcode: Refactor platform ID enumeration into a helper
Today, the only code that cares about the platform ID is the microcode
update code itself. To facilitate storing the platform ID in a more
generic place and using it outside of the microcode update itself, put
the enumeration into a helper function. Mirror
intel_get_microcode_revision()'s naming and location.
But, moving away from intel_collect_cpu_info() means that the model
and family information in CPUID is not readily available. Just call
CPUID again.
Note that the microcode header is a mask of supported platform IDs.
Only stick the ID part in the helper. Leave the 1<<id part in the
microcode handling.
Also note that the PII is weird. It does not really have a platform
ID because it doesn't even have the MSR. Just consider it to be
platform ID 0. Instead of saying >=PII, say <=PII. The PII is the
real oddball here being the only CPU with Linux microcode updates
but no platform ID. It's worth calling it out by name.
This does subtly change the sig->pf for the PII though from 0x0
to 0x1. Make up for that by ignoring sig->pf when the microcode
update platform mask is 0x0.
[ dhansen: reflow comment for bpetkov ]
--
Changes from v3:
* Handle the empty platform mask on the PII
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Link: https://patch.msgid.link/20260304181018.EB6404F8@davehans-spike.ostc.intel.com
---
arch/x86/kernel/cpu/microcode/intel.c | 54 ++++++++++++++++++++------
1 file changed, 43 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 8744f3a..83c6cd2 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -120,19 +120,44 @@ static inline unsigned int exttable_size(struct extended_sigtable *et)
return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
}
+
+/*
+ * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86
+ * structures are populated.
+ */
+static u32 intel_cpuid_vfm(void)
+{
+ u32 eax = cpuid_eax(1);
+ u32 fam = x86_family(eax);
+ u32 model = x86_model(eax);
+
+ return IFM(fam, model);
+}
+
+static u32 intel_get_platform_id(void)
+{
+ unsigned int val[2];
+
+ /*
+ * This can be called early. Use CPUID directly instead of
+ * relying on cpuinfo_x86 which may not be fully initialized.
+ * The PII does not have MSR_IA32_PLATFORM_ID. Everything
+ * before _it_ has no microcode (for Linux at least).
+ */
+ if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH)
+ return 0;
+
+ /* get processor flags from MSR 0x17 */
+ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+
+ return (val[1] >> 18) & 7;
+}
+
void intel_collect_cpu_info(struct cpu_signature *sig)
{
sig->sig = cpuid_eax(1);
- sig->pf = 0;
sig->rev = intel_get_microcode_revision();
-
- if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) {
- unsigned int val[2];
-
- /* get processor flags from MSR 0x17 */
- native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
- sig->pf = 1 << ((val[1] >> 18) & 7);
- }
+ sig->pf = 1 << intel_get_platform_id();
}
EXPORT_SYMBOL_GPL(intel_collect_cpu_info);
@@ -142,8 +167,15 @@ static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int s
if (s1->sig != sig2)
return false;
- /* Processor flags are either both 0 or they intersect. */
- return ((!s1->pf && !pf2) || (s1->pf & pf2));
+ /*
+ * Consider an empty mask to match everything. This
+ * should only occur for one CPU model, the PII.
+ */
+ if (!pf2)
+ return true;
+
+ /* Is the CPU's platform ID in the signature mask? */
+ return s1->pf & pf2;
}
bool intel_find_matching_signature(void *mc, struct cpu_signature *sig)© 2016 - 2026 Red Hat, Inc.