The VC3_SE2_CTRL_REG0_SE2_CLK_SEL macro is no longer used since
commit ae6040cd7c7f8 ("clk: versaclock3: Prepare for the addition of
5L35023 device"), which switched SE2 clock select handling to use
variant-specific OF data (se2_clk_sel_msk).
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v4 changes: None.
v3 changes:
- Added "Reviewed-by" tag from Fabrizio.
drivers/clk/clk-versaclock3.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
index 6dcf3d94db7b..18ef0f38c85b 100644
--- a/drivers/clk/clk-versaclock3.c
+++ b/drivers/clk/clk-versaclock3.c
@@ -61,7 +61,6 @@
#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3)
#define VC3_SE2_CTRL_REG0 0x1f
-#define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6)
#define VC3_SE3_DIFF1_CTRL_REG 0x21
#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6)
--
2.51.0