phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

[PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

Posted by Cristian Ciocaltea 1 month, 2 weeks ago

This series provides a set of bug fixes and cleanups for the Rockchip
Samsung HDPTX PHY driver.

The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
calculation and synchronization issues.  Specifically, it fixes edge
cases where the PHY PLL is pre-programmed by an external component (like
a bootloader) or when changing the color depth (bpc) while keeping the
modeline constant.  Because the Common Clock Framework .set_rate()
callback might not be invoked if the pixel clock remains unchanged, this
previously led to out-of-sync states between CCF and the actual HDMI PHY
configuration.

The second part focuses on code cleanups and modernizing the register
access.  Now that dw_hdmi_qp driver has fully switched to using
phy_configure(), we can drop the deprecated TMDS rate setup workarounds
and the restrict_rate_change flag logic.  Finally, it refactors the
driver to consistently use standard bitfield macros.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Cristian Ciocaltea (6):
      phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
      phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
      phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
      phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
      phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
      phy: rockchip: samsung-hdptx: Consistently use bitfield macros

 drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 215 +++++++++-------------
 1 file changed, 92 insertions(+), 123 deletions(-)
---
base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
change-id: 20260227-hdptx-clk-fixes-47426632f862

Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

Posted by 1und1 1 month, 2 weeks ago

Hi Cristian,

Am Freitag, dem 27.02.2026 um 22:48 +0200 schrieb Cristian Ciocaltea:
> This series provides a set of bug fixes and cleanups for the Rockchip
> Samsung HDPTX PHY driver.
> 
> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> calculation and synchronization issues.  Specifically, it fixes edge
> cases where the PHY PLL is pre-programmed by an external component (like
> a bootloader) or when changing the color depth (bpc) while keeping the
> modeline constant. 

as I brought up one of the mentioned edge cases with my Radxa Rock 5b booting
linux from EDK2 [1], I wanted to report that with this series applied,
everything works as expected and my issues are fixed.

Thus, feel free to add my

Tested-by: Thomas Niederprüm <dubito@online.de>

>  Because the Common Clock Framework .set_rate()
> callback might not be invoked if the pixel clock remains unchanged, this
> previously led to out-of-sync states between CCF and the actual HDMI PHY
> configuration.
> 
> The second part focuses on code cleanups and modernizing the register
> access.  Now that dw_hdmi_qp driver has fully switched to using
> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> and the restrict_rate_change flag logic.  Finally, it refactors the
> driver to consistently use standard bitfield macros.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> Cristian Ciocaltea (6):
>       phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc
>       phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
>       phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround
>       phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling
>       phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16()
>       phy: rockchip: samsung-hdptx: Consistently use bitfield macros
> 
>  drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 215 +++++++++------------
> -
>  1 file changed, 92 insertions(+), 123 deletions(-)
> ---
> base-commit: 7d6661873f6b54c75195780a40d66bad3d482d8f
> change-id: 20260227-hdptx-clk-fixes-47426632f862
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Best regards,

Thomas

[1]:
https://lore.kernel.org/lkml/b32164001947ba922aefb6ca86a8dc59e9323d2b.camel@online.de/

Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

Posted by Cristian Ciocaltea 1 month, 2 weeks ago

Hi Thomas,

On 3/2/26 9:46 PM, 1und1 wrote:
> Hi Cristian,
> 
> Am Freitag, dem 27.02.2026 um 22:48 +0200 schrieb Cristian Ciocaltea:
>> This series provides a set of bug fixes and cleanups for the Rockchip
>> Samsung HDPTX PHY driver.
>>
>> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
>> calculation and synchronization issues.  Specifically, it fixes edge
>> cases where the PHY PLL is pre-programmed by an external component (like
>> a bootloader) or when changing the color depth (bpc) while keeping the
>> modeline constant. 
> 
> as I brought up one of the mentioned edge cases with my Radxa Rock 5b booting
> linux from EDK2 [1], I wanted to report that with this series applied,
> everything works as expected and my issues are fixed.
> 
> Thus, feel free to add my
> 
> Tested-by: Thomas Niederprüm <dubito@online.de>

Thanks for (re)testing!

Regards,
Cristian