On a arm64 platform, there is a 10~11ms gap during PCI bus scan(last two
line below, between 0000:01:00.0 and 0000:02:00.0):
[    0.078871] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff window]
[    0.078873] pci_bus 0000:00: root bus resource [mem 0x1000000000-0x1fffffffff window]
[    0.078875] pci_bus 0000:00: root bus resource [io  0x0000-0xffff window]
[    0.078877] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.078888] pci 0000:00:00.0: [1db7:dc01] type 01 class 0x060400
[    0.078895] pci 0000:00:00.0: reg 0x38: [mem 0xfff00000-0xffffffff pref]
[    0.078914] pci 0000:00:00.0: supports D1
[    0.078916] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    0.078979] pci 0000:00:01.0: [1db7:dc01] type 01 class 0x060400
[    0.078984] pci 0000:00:01.0: reg 0x10: [mem 0x1000000000-0x10000fffff 64bit pref]
[    0.079001] pci 0000:00:01.0: supports D1 D2
[    0.079003] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.079073] pci 0000:01:00.0: [1e49:1101] type 00 class 0x010802
[    0.079086] pci 0000:01:00.0: reg 0x10: [mem 0x58100000-0x58103fff 64bit]
[    0.079201] pci 0000:01:00.0: 31.504 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x4 link at 0000:00:00.0 (capable ojjf 63.012 Gb/s with 16.0 GT/s PCIe x4 link)
[    0.091501] pci 0000:02:00.0: [10ec:b852] type 00 class 0x028000

In pcie_wait_for_link_status(), using msleep(1) to wait for link status
change.
But msleep(1) can sleep for nearly 5ms.

ftrace shows:
 0)               |                pcie_wait_for_link_status() {
 0)   0.500 us    |                  pcie_capability_read_word();
 0)   0.580 us    |                  pcie_capability_read_word();
 0) * 10292.26 us |                }

 after changing to usleep_range().
 ftrace shows:

 0)               |                pcie_wait_for_link_status() {
 0)   0.320 us    |                  pcie_capability_read_word();
 0)   0.480 us    |                  pcie_capability_read_word();
 0) # 2483.980 us |                }

 After changing to usleep_range(), the time gap is gone:
 ...
[    0.076763] PCI host bridge to bus 0000:00
[    0.076766] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff window]
[    0.076768] pci_bus 0000:00: root bus resource [mem 0x1000000000-0x1fffffffff window]
[    0.076770] pci_bus 0000:00: root bus resource [io  0x0000-0xffff window]
[    0.076772] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.076783] pci 0000:00:00.0: [1db7:dc01] type 01 class 0x060400
[    0.076791] pci 0000:00:00.0: reg 0x38: [mem 0xfff00000-0xffffffff pref]
[    0.076811] pci 0000:00:00.0: supports D1
[    0.076813] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    0.076874] pci 0000:00:01.0: [1db7:dc01] type 01 class 0x060400
[    0.076880] pci 0000:00:01.0: reg 0x10: [mem 0x1000000000-0x10000fffff 64bit pref]
[    0.076897] pci 0000:00:01.0: supports D1 D2
[    0.076898] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.076969] pci 0000:01:00.0: [1e49:1101] type 00 class 0x010802
[    0.076982] pci 0000:01:00.0: reg 0x10: [mem 0x58100000-0x58103fff 64bit]
[    0.077098] pci 0000:01:00.0: 31.504 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x4 link at 0000:00:00.0 (capable of 63.012 Gb/s with 16.0 GT/s PCIe x4 link)
[    0.078281] pci 0000:02:00.0: [10ec:b852] type 00 class 0x028000

To speed up booting, replace msleep() by using fsleep() (more generic
then usleep_range()).

Signed-off-by: Hongyu Xie <xiehongyu1@kylinos.cn>
---

v2->v1:
1, add booting log
2, change usleep_range to fsleep

 drivers/pci/pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f3244630bfd0..15fd15f24df3 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4519,7 +4519,7 @@ static int pcie_wait_for_link_status(struct pci_dev *pdev,
 		pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
 		if ((lnksta & lnksta_mask) == lnksta_match)
 			return 0;
-		msleep(1);
+		fsleep(1000);
 	} while (time_before(jiffies, end_jiffies));
 
 	return -ETIMEDOUT;
-- 
2.25.1