Add the bindings for Neutron, a Neural Processing Unit from NXP.
Signed-off-by: Jiwei Fu <jiwei.fu@nxp.com>
Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
---
.../devicetree/bindings/npu/nxp,imx95-neutron.yaml | 95 ++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml b/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml
new file mode 100644
index 000000000000..ba1f6851866b
--- /dev/null
+++ b/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/npu/nxp,imx95-neutron.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Neutron NPU
+
+maintainers:
+ - Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
+ - Jiwei Fu <jiwei.fu@nxp.com>
+
+description:
+ Neutron is an NPU from NXP targeting edge AI inference applications.
+ Initially supported on i.MX95 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - nxp,imx95-neutron
+
+ reg:
+ items:
+ - description: Register space
+ - description: Instruction area of the TCM space
+ - description: Data area of the TCM space
+
+ reg-names:
+ items:
+ - const: regs
+ - const: itcm
+ - const: dtcm
+
+ memory-region:
+ description:
+ Phandle referencing a "shared-dma-pool" to be used for Neutron
+ inference buffers, which need to be 1MB aligned.
+
+ The memory region must be defined with alignment of 1MB and size
+ should be large enough to accommodate the targeted ML models. It
+ should be marked as reusable.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: npu
+ - const: npu_apb
+ - const: npu_cgc
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - memory-region
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ neutron@4ab00000 {
+ compatible = "nxp,imx95-neutron";
+ reg = <0x0 0x4ab00000 0x0 0x00000400>,
+ <0x0 0x4AB10000 0x0 0x00010000>,
+ <0x0 0x4AB08000 0x0 0x00008000>;
+ reg-names = "regs", "itcm", "dtcm";
+ memory-region = <&neutron_pool>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 68>, <&scmi_clk 67>;
+ clock-names = "npu", "npu_apb";
+ power-domains = <&scmi_devpd 20>;
+ };
+ };
+...
--
2.34.1On 26/02/2026 14:40, Ioana Ciocoi-Radulescu wrote:
A nit, subject: drop second/last, redundant "bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> +
> + memory-region:
> + description:
> + Phandle referencing a "shared-dma-pool" to be used for Neutron
> + inference buffers, which need to be 1MB aligned.
> +
> + The memory region must be defined with alignment of 1MB and size
> + should be large enough to accommodate the targeted ML models. It
> + should be marked as reusable.
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
Why is this flexible?
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: npu
Name "npu" is pretty pointless.
> + - const: npu_apb
> + - const: npu_cgc
Drop npu perfix everywhere.
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - memory-region
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + neutron@4ab00000 {
> + compatible = "nxp,imx95-neutron";
Messed indentation. Read writing bindings / writing schema.
Best regards,
Krzysztof
On Thu, Feb 26, 2026 at 03:40:42PM +0200, Ioana Ciocoi-Radulescu wrote:
> Add the bindings for Neutron, a Neural Processing Unit from NXP.
>
> Signed-off-by: Jiwei Fu <jiwei.fu@nxp.com>
You are the author and submitter. What did Jiwei do?
> Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
> ---
> .../devicetree/bindings/npu/nxp,imx95-neutron.yaml | 95 ++++++++++++++++++++++
> 1 file changed, 95 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml b/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml
> new file mode 100644
> index 000000000000..ba1f6851866b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/npu/nxp,imx95-neutron.yaml
> @@ -0,0 +1,95 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/npu/nxp,imx95-neutron.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP Neutron NPU
> +
> +maintainers:
> + - Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
> + - Jiwei Fu <jiwei.fu@nxp.com>
> +
> +description:
> + Neutron is an NPU from NXP targeting edge AI inference applications.
> + Initially supported on i.MX95 SoCs.
> +
> +properties:
> + compatible:
> + enum:
> + - nxp,imx95-neutron
> +
> + reg:
> + items:
> + - description: Register space
> + - description: Instruction area of the TCM space
> + - description: Data area of the TCM space
> +
> + reg-names:
> + items:
> + - const: regs
> + - const: itcm
> + - const: dtcm
> +
> + memory-region:
> + description:
> + Phandle referencing a "shared-dma-pool" to be used for Neutron
> + inference buffers, which need to be 1MB aligned.
> +
> + The memory region must be defined with alignment of 1MB and size
> + should be large enough to accommodate the targeted ML models. It
> + should be marked as reusable.
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: npu
> + - const: npu_apb
> + - const: npu_cgc
clocks should be done as reg is, with the descriptions in the !-names
property. Not really keen on the names either, these are all npu clocks
so the npu prefix is odd.
Additionally, why is the number of clocks variable when you only have
one platform?
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - memory-region
> + - interrupts
Odd that clocks are not mandatory!
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + neutron@4ab00000 {
"neutron" is not a generic node name. This should be something like
"accelerator" or similar.
pw-bot: changes-requested
Cheers,
Conor.
> + compatible = "nxp,imx95-neutron";
> + reg = <0x0 0x4ab00000 0x0 0x00000400>,
> + <0x0 0x4AB10000 0x0 0x00010000>,
> + <0x0 0x4AB08000 0x0 0x00008000>;
> + reg-names = "regs", "itcm", "dtcm";
> + memory-region = <&neutron_pool>;
> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk 68>, <&scmi_clk 67>;
> + clock-names = "npu", "npu_apb";
> + power-domains = <&scmi_devpd 20>;
> + };
> + };
> +...
>
> --
> 2.34.1
>
On 2/26/26 20:20, Conor Dooley wrote:
[..]
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> + bus {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + neutron@4ab00000 {
> "neutron" is not a generic node name. This should be something like
> "accelerator" or similar.
>
The only dts nodes I could find using accel subsystem are from rockhip. And they use npu@
e.g:
» rknn_core_0: npu@fdab0000 {
» » compatible = "rockchip,rk3588-rknn-core";
Also, Ethos-U64 introduced by Rob with [1] is using npu@.
So, I think we should go wit that. I haven't seen any document to standardize the naming.
[1] https://www.spinics.net/lists/kernel/msg6055856.html
On Fri, Feb 27, 2026 at 08:45:29AM +0200, Daniel Baluta wrote:
> On 2/26/26 20:20, Conor Dooley wrote:
> [..]
> >> + - |
> >> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> + #include <dt-bindings/interrupt-controller/irq.h>
> >> +
> >> + bus {
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >> + neutron@4ab00000 {
> > "neutron" is not a generic node name. This should be something like
> > "accelerator" or similar.
> >
> The only dts nodes I could find using accel subsystem are from rockhip. And they use npu@
>
> e.g:
>
> » rknn_core_0: npu@fdab0000 {
> » » compatible = "rockchip,rk3588-rknn-core";
>
> Also, Ethos-U64 introduced by Rob with [1] is using npu@.
>
> So, I think we should go wit that. I haven't seen any document to standardize the naming.
accelerator, npu, makes no difference to me, so sure.
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