This clk driver has a noop determine_rate clk op. Drop this empty
function, and enable the CLK_ROUNDING_FW_MANAGED flag.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
To: Geert Uytterhoeven <geert+renesas@glider.be>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
drivers/clk/renesas/rzg2l-cpg.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c0584bab58a3ba8a637e77662191f89a57bf1390..126398267e60d1f0fa7ababcb22a5c540884e810 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
return pll5_rate;
}
-static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return 0;
-}
-
static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
@@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
static const struct clk_ops rzg2l_cpg_sipll5_ops = {
.recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
- .determine_rate = rzg2l_cpg_sipll5_determine_rate,
.set_rate = rzg2l_cpg_sipll5_set_rate,
};
@@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
init.name = core->name;
parent_name = __clk_get_name(parent);
init.ops = &rzg2l_cpg_sipll5_ops;
- init.flags = 0;
+ init.flags = CLK_ROUNDING_FW_MANAGED;
init.parent_names = &parent_name;
init.num_parents = 1;
--
2.53.0Hi Brian,
C Biju
On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> This clk driver has a noop determine_rate clk op. Drop this empty
> function, and enable the CLK_ROUNDING_FW_MANAGED flag.
>
> Signed-off-by: Brian Masney <bmasney@redhat.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> return pll5_rate;
> }
>
> -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
> - struct clk_rate_request *req)
> -{
> - return 0;
> -}
> -
> static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> unsigned long rate,
> unsigned long parent_rate)
> @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
>
> static const struct clk_ops rzg2l_cpg_sipll5_ops = {
> .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
> - .determine_rate = rzg2l_cpg_sipll5_determine_rate,
> .set_rate = rzg2l_cpg_sipll5_set_rate,
> };
>
> @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> init.name = core->name;
> parent_name = __clk_get_name(parent);
> init.ops = &rzg2l_cpg_sipll5_ops;
> - init.flags = 0;
> + init.flags = CLK_ROUNDING_FW_MANAGED;
Iff this is the Right Thing To Do (TM), it needs a comment, as this
clock is not managed by firmware.
> init.parent_names = &parent_name;
> init.num_parents = 1;
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > This clk driver has a noop determine_rate clk op. Drop this empty
> > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> >
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> > return pll5_rate;
> > }
> >
> > -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
> > - struct clk_rate_request *req)
> > -{
> > - return 0;
> > -}
> > -
> > static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> > unsigned long rate,
> > unsigned long parent_rate)
> > @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> >
> > static const struct clk_ops rzg2l_cpg_sipll5_ops = {
> > .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
> > - .determine_rate = rzg2l_cpg_sipll5_determine_rate,
> > .set_rate = rzg2l_cpg_sipll5_set_rate,
> > };
> >
> > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > init.name = core->name;
> > parent_name = __clk_get_name(parent);
> > init.ops = &rzg2l_cpg_sipll5_ops;
> > - init.flags = 0;
> > + init.flags = CLK_ROUNDING_FW_MANAGED;
>
> Iff this is the Right Thing To Do (TM), it needs a comment, as this
> clock is not managed by firmware.
Before I start a larger discussion on patch 1 with more people about a
name for this flag, help me understand why this provider has a noop
determine rate. Is the hardware eventually programmed with a rate
that's close enough to what was passed in? Or it doesn't really matter
what the clock rate is, just as long as it is running? Or should the
determine_rate function be filled out in this particular case?
Thanks,
Brian
Hi Brian,
On Fri, 27 Feb 2026 at 16:01, Brian Masney <bmasney@redhat.com> wrote:
> On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> > On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > > This clk driver has a noop determine_rate clk op. Drop this empty
> > > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> > >
> > > Signed-off-by: Brian Masney <bmasney@redhat.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > > init.name = core->name;
> > > parent_name = __clk_get_name(parent);
> > > init.ops = &rzg2l_cpg_sipll5_ops;
> > > - init.flags = 0;
> > > + init.flags = CLK_ROUNDING_FW_MANAGED;
> >
> > Iff this is the Right Thing To Do (TM), it needs a comment, as this
> > clock is not managed by firmware.
>
> Before I start a larger discussion on patch 1 with more people about a
> name for this flag, help me understand why this provider has a noop
> determine rate. Is the hardware eventually programmed with a rate
> that's close enough to what was passed in? Or it doesn't really matter
> what the clock rate is, just as long as it is running? Or should the
> determine_rate function be filled out in this particular case?
I'd like to defer to Biju, who added the empty round^Wdetermine rate
function.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Feb 27, 2026 at 09:20:09AM +0100, Geert Uytterhoeven wrote:
> On Thu, 26 Feb 2026 at 19:18, Brian Masney <bmasney@redhat.com> wrote:
> > This clk driver has a noop determine_rate clk op. Drop this empty
> > function, and enable the CLK_ROUNDING_FW_MANAGED flag.
> >
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -938,12 +938,6 @@ static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> > return pll5_rate;
> > }
> >
> > -static int rzg2l_cpg_sipll5_determine_rate(struct clk_hw *hw,
> > - struct clk_rate_request *req)
> > -{
> > - return 0;
> > -}
> > -
> > static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> > unsigned long rate,
> > unsigned long parent_rate)
> > @@ -1015,7 +1009,6 @@ static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> >
> > static const struct clk_ops rzg2l_cpg_sipll5_ops = {
> > .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
> > - .determine_rate = rzg2l_cpg_sipll5_determine_rate,
> > .set_rate = rzg2l_cpg_sipll5_set_rate,
> > };
> >
> > @@ -1041,7 +1034,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
> > init.name = core->name;
> > parent_name = __clk_get_name(parent);
> > init.ops = &rzg2l_cpg_sipll5_ops;
> > - init.flags = 0;
> > + init.flags = CLK_ROUNDING_FW_MANAGED;
>
> Iff this is the Right Thing To Do (TM), it needs a comment, as this
> clock is not managed by firmware.
It needs a better name for the flag. I'll reply on patch 1 where more
people are CCed to see if we can come up with a better idea.
Brian
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