Convert RAMC SDRAM/DDR controller binding to YAML format.
Signed-off-by: Akhila YS <akhilayalmati@gmail.com>
---
.../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 ++++++++++++++++++++++
.../devicetree/bindings/arm/atmel-sysregs.txt | 20 -------
2 files changed, 67 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml
new file mode 100644
index 000000000000..1516fc8e09e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Claudiu Beznea <claudiu.beznea@tuxon.dev>
+
+description:
+ The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
+ Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
+ SDRAM / DDR memory. It is typically exposed as a syscon node for
+ register access from other drivers (e.g. for initialization or mode
+ configuration). No interrupts or clocks are usually required in the
+ binding.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: atmel,at91rm9200-sdramc
+ - const: syscon
+ - items:
+ - const: microchip,sama7d65-uddrc
+ - const: microchip,sama7g5-uddrc
+ - items:
+ enum:
+ - atmel,at91sam9260-sdramc
+ - atmel,at91sam9g45-ddramc
+ - atmel,sama5d3-ddramc
+ - microchip,sam9x60-ddramc
+ - microchip,sam9x7-ddramc
+ - microchip,sama7g5-uddrc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ddrck
+ - const: mpddr
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+ ramc@ffffe400 {
+ compatible = "atmel,at91sam9g45-ddramc";
+ reg = <0xffffe400 0x200>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>;
+ clock-names = "ddrck";
+ };
+...
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
deleted file mode 100644
index 14642384bc87..000000000000
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Atmel system registers
-
-RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or
- "atmel,at91sam9260-sdramc" or
- "atmel,at91sam9g45-ddramc" or
- "atmel,sama5d3-ddramc" or
- "microchip,sam9x60-ddramc" or
- "microchip,sama7g5-uddrc" or
- "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or
- "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
-- reg: Should contain registers location and length
-
-Examples:
-
- ramc0: ramc@ffffe800 {
- compatible = "atmel,at91sam9g45-ddramc";
- reg = <0xffffe800 0x200>;
- };
-
--
2.43.0On Thu, Feb 26, 2026 at 04:13:37PM +0000, Akhila YS wrote: > Convert RAMC SDRAM/DDR controller binding to YAML format. > > Signed-off-by: Akhila YS <akhilayalmati@gmail.com> > --- > .../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 ++++++++++++++++++++++ > .../devicetree/bindings/arm/atmel-sysregs.txt | 20 ------- > 2 files changed, 67 insertions(+), 20 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml > new file mode 100644 > index 000000000000..1516fc8e09e1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC) > + > +maintainers: > + - Nicolas Ferre <nicolas.ferre@microchip.com> > + - Claudiu Beznea <claudiu.beznea@tuxon.dev> > + > +description: > + The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various > + Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external > + SDRAM / DDR memory. It is typically exposed as a syscon node for > + register access from other drivers (e.g. for initialization or mode > + configuration). No interrupts or clocks are usually required in the > + binding. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: atmel,at91rm9200-sdramc > + - const: syscon > + - items: > + - const: microchip,sama7d65-uddrc > + - const: microchip,sama7g5-uddrc > + - items: > + enum: Whoops, sorry for not noticing this earlier, but an items list with one entry can be reduced to that one entry. For you here that means that "- items enum:" becomes "- enum:".
On 26-02-2026 23:42, Conor Dooley wrote: > On Thu, Feb 26, 2026 at 04:13:37PM +0000, Akhila YS wrote: >> Convert RAMC SDRAM/DDR controller binding to YAML format. >> >> Signed-off-by: Akhila YS <akhilayalmati@gmail.com> >> --- >> .../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 ++++++++++++++++++++++ >> .../devicetree/bindings/arm/atmel-sysregs.txt | 20 ------- >> 2 files changed, 67 insertions(+), 20 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml >> new file mode 100644 >> index 000000000000..1516fc8e09e1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml >> @@ -0,0 +1,67 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC) >> + >> +maintainers: >> + - Nicolas Ferre <nicolas.ferre@microchip.com> >> + - Claudiu Beznea <claudiu.beznea@tuxon.dev> >> + >> +description: >> + The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various >> + Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external >> + SDRAM / DDR memory. It is typically exposed as a syscon node for >> + register access from other drivers (e.g. for initialization or mode >> + configuration). No interrupts or clocks are usually required in the >> + binding. >> + >> +properties: >> + compatible: >> + oneOf: >> + - items: >> + - const: atmel,at91rm9200-sdramc >> + - const: syscon >> + - items: >> + - const: microchip,sama7d65-uddrc >> + - const: microchip,sama7g5-uddrc >> + - items: >> + enum: > Whoops, sorry for not noticing this earlier, but an items list with one > entry can be reduced to that one entry. For you here that means that > "- items enum:" becomes "- enum:". Hi, i changed patch as per your suggestion, but i found some errors with dtbs_check, anyway i sent a v4 patch. let me know if any changes required. -- Best Regards, Akhila.
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