This series adds support for the NVIDIA Tegra264 UART controller, which
is derived from the AMBA PL011.

On Tegra264, the fractional baud rate divisor (FBRD) register is
broken. Configuring the baud rate using IBRD and FBRD may result in the
baud rate falling outside the required tolerance. Instead, the baud
rate is derived by setting the UART clock.

The following vendor flags are introduced:
 - skip_ibrd_fbrd: to skip IBRD/FBRD programming
 - set_uartclk_rate: to configure the baud rate by setting the UART
   clock rate

Additionally, some DMA controllers (e.g. Tegra GPCDMA) require transfer
lengths to satisfy the controller's copy_align constraint. The PL011
driver does not currently enforce this, which can result in rejected
transfers. The DMA alignment change aligns the TX DMA length down to
the required boundary, with any remaining bytes handled via the
existing PIO fallback.

Kartik Rajput (4):
  serial: amba-pl011: Introduce skip_ibrd_fbrd vendor flag
  serial: amba-pl011: Introduce set_uartclk_rate vendor flag
  serial: amba-pl011: Add Tegra264 UART support
  serial: amba-pl011: Respect DMA controller's copy_align requirement

 drivers/tty/serial/amba-pl011.c | 118 +++++++++++++++++++++++++-------
 1 file changed, 94 insertions(+), 24 deletions(-)

-- 
2.43.0