For some reason we ended with incorrect register offset for soundwire tx
controller reset and the regmap register max was also incorrect it was
0x1000 instead of 0x12000 which is full register range for this IP.

This was somehow compenseated in DT reg property which got it working so
far.

Fix this by correcting the actual offset and max registers as per SoC
documentation.

Fixes: b076b995e225 ("clk: qcom: Add SM6115 LPASSCC")
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
---
 drivers/clk/qcom/lpasscc-sm6115.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/lpasscc-sm6115.c b/drivers/clk/qcom/lpasscc-sm6115.c
index ac6d219233b4..47adf4de2cca 100644
--- a/drivers/clk/qcom/lpasscc-sm6115.c
+++ b/drivers/clk/qcom/lpasscc-sm6115.c
@@ -35,7 +35,7 @@ static const struct qcom_cc_desc lpass_audiocc_sm6115_reset_desc = {
 };
 
 static const struct qcom_reset_map lpasscc_sm6115_resets[] = {
-	[LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0x100, .bit = 1, .udelay = 500 },
+	[LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0xc100, .bit = 1, .udelay = 500 },
 };
 
 static struct regmap_config lpasscc_sm6115_regmap_config = {
@@ -43,7 +43,7 @@ static struct regmap_config lpasscc_sm6115_regmap_config = {
 	.reg_stride = 4,
 	.val_bits = 32,
 	.name = "lpass-tcsr",
-	.max_register = 0x1000,
+	.max_register = 0x12000,
 };
 
 static const struct qcom_cc_desc lpasscc_sm6115_reset_desc = {
-- 
2.47.3

On 2/23/26 2:39 PM, Srinivas Kandagatla wrote:
> For some reason we ended with incorrect register offset for soundwire tx
> controller reset and the regmap register max was also incorrect it was
> 0x1000 instead of 0x12000 which is full register range for this IP.
> 
> This was somehow compenseated in DT reg property which got it working so
> far.
> 
> Fix this by correcting the actual offset and max registers as per SoC
> documentation.
> 
> Fixes: b076b995e225 ("clk: qcom: Add SM6115 LPASSCC")
> Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/lpasscc-sm6115.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/qcom/lpasscc-sm6115.c b/drivers/clk/qcom/lpasscc-sm6115.c
> index ac6d219233b4..47adf4de2cca 100644
> --- a/drivers/clk/qcom/lpasscc-sm6115.c
> +++ b/drivers/clk/qcom/lpasscc-sm6115.c
> @@ -35,7 +35,7 @@ static const struct qcom_cc_desc lpass_audiocc_sm6115_reset_desc = {
>  };
>  
>  static const struct qcom_reset_map lpasscc_sm6115_resets[] = {
> -	[LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0x100, .bit = 1, .udelay = 500 },
> +	[LPASS_SWR_TX_CONFIG_CGCR] = { .reg = 0xc100, .bit = 1, .udelay = 500 },

So after taking a deeper dive, we currently define CGCR "resets" with bit(1)

The CGCRs ("Clock Gating Control Registers") have:

BIT(1) HW_CTL
BIT(0) CLK_ENABLE

so by ""asserting"" the resets, we really put the *clocks* in HW CTL mode
(that's why drivers/soundwire/qcom.c only ever calls reset_control_reset()
and during "configure"-type sequences)

I think for not making a mess out of backwards compatiblity, we could stay
with this model, but we should def write it down somewhere..

I don't know if we ever need to manually assert CLK_ENABLE from Linux.


Now, interestingly, msm-4.19 techpack/audio has this hunk:

/* SW workaround to gate hw_ctl for SWR version >=1.6 */
if (swrm->version >= SWRM_VERSION_1_6) {
        if (swrm->swrm_hctl_reg) {
                temp = ioread32(swrm->swrm_hctl_reg);
                temp &= 0xFFFFFFFD;
                iowrite32(temp, swrm->swrm_hctl_reg);
                usleep_range(500, 505);
                temp = ioread32(swrm->swrm_hctl_reg);
                dev_dbg(swrm->dev, "%s: hctl_reg val: 0x%x\n",
                        __func__, temp);
        }
}

which clears that hw_ctl bit

Konrad