When available use the immediate variant of RDMSR in __rdmsr().
For the safe/unsafe variants make __rdmsr() to be a common base
function instead of duplicating the ALTERNATIVE*() macros.
Modify native_rdmsr() and native_read_msr() to use native_rdmsrq().
The paravirt case will be handled later.
Originally-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
V2:
- new patch, partially taken from "[RFC PATCH v2 22/34] x86/msr: Utilize
the alternatives mechanism to read MSR" by Xin Li
---
arch/x86/include/asm/msr.h | 116 ++++++++++++++++++++++++++++---------
1 file changed, 89 insertions(+), 27 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index ba11c3375cbd..990268dea5ad 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -65,6 +65,8 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {}
/* The GNU Assembler (Gas) with Binutils 2.41 adds the .insn directive support */
#if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >= 24100
+#define ASM_RDMSR_IMM \
+ " .insn VEX.128.F2.M7.W0 0xf6 /0, %[msr]%{:u32}, %[val]\n\t"
#define ASM_WRMSRNS_IMM \
" .insn VEX.128.F3.M7.W0 0xf6 /0, %[val], %[msr]%{:u32}\n\t"
#else
@@ -74,10 +76,17 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {}
* The register operand is encoded as %rax because all uses of the immediate
* form MSR access instructions reference %rax as the register operand.
*/
+#define ASM_RDMSR_IMM \
+ " .byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]"
#define ASM_WRMSRNS_IMM \
" .byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]"
#endif
+#define RDMSR_AND_SAVE_RESULT \
+ "rdmsr\n\t" \
+ "shl $0x20, %%rdx\n\t" \
+ "or %%rdx, %%rax\n\t"
+
#define PREPARE_RDX_FOR_WRMSR \
"mov %%rax, %%rdx\n\t" \
"shr $0x20, %%rdx\n\t"
@@ -93,16 +102,76 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {}
* think of extending them - you will be slapped with a stinking trout or a frozen
* shark will reach you, wherever you are! You've been warned.
*/
-static __always_inline u64 __rdmsr(u32 msr)
+static __always_inline bool __rdmsrq_variable(u32 msr, u64 *val, int type)
+ {
+#ifdef CONFIG_X86_64
+ BUILD_BUG_ON(__builtin_constant_p(msr));
+
+ asm_inline volatile goto(
+ "1:\n"
+ RDMSR_AND_SAVE_RESULT
+ _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */
+
+ : [val] "=a" (*val)
+ : "c" (msr), [type] "i" (type)
+ : "rdx"
+ : badmsr);
+#else
+ asm_inline volatile goto(
+ "1: rdmsr\n\t"
+ _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */
+
+ : "=A" (*val)
+ : "c" (msr), [type] "i" (type)
+ :
+ : badmsr);
+#endif
+
+ return false;
+
+badmsr:
+ *val = 0;
+
+ return true;
+}
+
+#ifdef CONFIG_X86_64
+static __always_inline bool __rdmsrq_constant(u32 msr, u64 *val, int type)
{
- EAX_EDX_DECLARE_ARGS(val, low, high);
+ BUILD_BUG_ON(!__builtin_constant_p(msr));
- asm volatile("1: rdmsr\n"
- "2:\n"
- _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR)
- : EAX_EDX_RET(val, low, high) : "c" (msr));
+ asm_inline volatile goto(
+ "1:\n"
+ ALTERNATIVE("mov %[msr], %%ecx\n\t"
+ "2:\n"
+ RDMSR_AND_SAVE_RESULT,
+ ASM_RDMSR_IMM,
+ X86_FEATURE_MSR_IMM)
+ _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR immediate */
+ _ASM_EXTABLE_TYPE(2b, %l[badmsr], %c[type]) /* For RDMSR */
+
+ : [val] "=a" (*val)
+ : [msr] "i" (msr), [type] "i" (type)
+ : "ecx", "rdx"
+ : badmsr);
- return EAX_EDX_VAL(val, low, high);
+ return false;
+
+badmsr:
+ *val = 0;
+
+ return true;
+}
+#endif
+
+static __always_inline bool __rdmsr(u32 msr, u64 *val, int type)
+{
+#ifdef CONFIG_X86_64
+ if (__builtin_constant_p(msr))
+ return __rdmsrq_constant(msr, val, type);
+#endif
+
+ return __rdmsrq_variable(msr, val, type);
}
static __always_inline bool __wrmsrq_variable(u32 msr, u64 val, int type)
@@ -177,18 +246,22 @@ static __always_inline bool __wrmsrq(u32 msr, u64 val, int type)
return __wrmsrq_variable(msr, val, type);
}
+static __always_inline u64 native_rdmsrq(u32 msr)
+{
+ u64 val;
+
+ __rdmsr(msr, &val, EX_TYPE_RDMSR);
+
+ return val;
+}
+
#define native_rdmsr(msr, val1, val2) \
do { \
- u64 __val = __rdmsr((msr)); \
+ u64 __val = native_rdmsrq((msr)); \
(void)((val1) = (u32)__val); \
(void)((val2) = (u32)(__val >> 32)); \
} while (0)
-static __always_inline u64 native_rdmsrq(u32 msr)
-{
- return __rdmsr(msr);
-}
-
static __always_inline void native_wrmsrq(u32 msr, u64 val)
{
__wrmsrq(msr, val, EX_TYPE_WRMSR);
@@ -201,23 +274,12 @@ static __always_inline void native_wrmsr(u32 msr, u32 low, u32 high)
static inline u64 native_read_msr(u32 msr)
{
- return __rdmsr(msr);
+ return native_rdmsrq(msr);
}
-static inline int native_read_msr_safe(u32 msr, u64 *p)
+static inline int native_read_msr_safe(u32 msr, u64 *val)
{
- int err;
- EAX_EDX_DECLARE_ARGS(val, low, high);
-
- asm volatile("1: rdmsr ; xor %[err],%[err]\n"
- "2:\n\t"
- _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err])
- : [err] "=r" (err), EAX_EDX_RET(val, low, high)
- : "c" (msr));
-
- *p = EAX_EDX_VAL(val, low, high);
-
- return err;
+ return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0;
}
/* Can be uninlined because referenced by paravirt */
--
2.53.0Hi Juergen,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.19 next-20260218]
[cannot apply to tip/x86/core kvm/queue kvm/next kvm/linux-next tip/x86/tdx]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Juergen-Gross/x86-alternative-Support-alt_replace_call-with-instructions-after-call/20260218-163031
base: linus/master
patch link: https://lore.kernel.org/r/20260218082133.400602-11-jgross%40suse.com
patch subject: [PATCH v3 10/16] x86/msr: Use the alternatives mechanism for RDMSR
config: x86_64-randconfig-076-20260218 (https://download.01.org/0day-ci/archive/20260218/202602182222.WEBLSQRj-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260218/202602182222.WEBLSQRj-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602182222.WEBLSQRj-lkp@intel.com/
All errors (new ones prefixed by >>):
arch/x86/hyperv/hv_crash.c: In function 'hv_hvcrash_ctxt_save':
>> arch/x86/hyperv/hv_crash.c:216:24: error: too few arguments to function '__rdmsr'
216 | ctxt->gsbase = __rdmsr(MSR_GS_BASE);
| ^~~~~~~
In file included from arch/x86/include/asm/tsc.h:11,
from arch/x86/include/asm/timex.h:6,
from include/linux/timex.h:67,
from include/linux/time32.h:13,
from include/linux/time.h:60,
from include/linux/jiffies.h:10,
from include/linux/delay.h:14,
from arch/x86/hyperv/hv_crash.c:40:
arch/x86/include/asm/msr.h:167:29: note: declared here
167 | static __always_inline bool __rdmsr(u32 msr, u64 *val, int type)
| ^~~~~~~
arch/x86/hyperv/hv_crash.c:217:22: error: too few arguments to function '__rdmsr'
217 | ctxt->efer = __rdmsr(MSR_EFER);
| ^~~~~~~
arch/x86/include/asm/msr.h:167:29: note: declared here
167 | static __always_inline bool __rdmsr(u32 msr, u64 *val, int type)
| ^~~~~~~
arch/x86/hyperv/hv_crash.c:218:21: error: too few arguments to function '__rdmsr'
218 | ctxt->pat = __rdmsr(MSR_IA32_CR_PAT);
| ^~~~~~~
arch/x86/include/asm/msr.h:167:29: note: declared here
167 | static __always_inline bool __rdmsr(u32 msr, u64 *val, int type)
| ^~~~~~~
arch/x86/hyperv/hv_crash.c: In function 'crash_nmi_callback':
arch/x86/hyperv/hv_crash.c:282:13: warning: variable 'status' set but not used [-Wunused-but-set-variable]
282 | u64 status;
| ^~~~~~
vim +/__rdmsr +216 arch/x86/hyperv/hv_crash.c
94212d34618c26 Mukesh Rathor 2025-10-06 192
94212d34618c26 Mukesh Rathor 2025-10-06 193 /* Save essential context */
94212d34618c26 Mukesh Rathor 2025-10-06 194 static void hv_hvcrash_ctxt_save(void)
94212d34618c26 Mukesh Rathor 2025-10-06 195 {
94212d34618c26 Mukesh Rathor 2025-10-06 196 struct hv_crash_ctxt *ctxt = &hv_crash_ctxt;
94212d34618c26 Mukesh Rathor 2025-10-06 197
94212d34618c26 Mukesh Rathor 2025-10-06 198 asm volatile("movq %%rsp,%0" : "=m"(ctxt->rsp));
94212d34618c26 Mukesh Rathor 2025-10-06 199
94212d34618c26 Mukesh Rathor 2025-10-06 200 ctxt->cr0 = native_read_cr0();
94212d34618c26 Mukesh Rathor 2025-10-06 201 ctxt->cr4 = native_read_cr4();
94212d34618c26 Mukesh Rathor 2025-10-06 202
94212d34618c26 Mukesh Rathor 2025-10-06 203 asm volatile("movq %%cr2, %0" : "=a"(ctxt->cr2));
94212d34618c26 Mukesh Rathor 2025-10-06 204 asm volatile("movq %%cr8, %0" : "=a"(ctxt->cr8));
94212d34618c26 Mukesh Rathor 2025-10-06 205
94212d34618c26 Mukesh Rathor 2025-10-06 206 asm volatile("movl %%cs, %%eax" : "=a"(ctxt->cs));
94212d34618c26 Mukesh Rathor 2025-10-06 207 asm volatile("movl %%ss, %%eax" : "=a"(ctxt->ss));
94212d34618c26 Mukesh Rathor 2025-10-06 208 asm volatile("movl %%ds, %%eax" : "=a"(ctxt->ds));
94212d34618c26 Mukesh Rathor 2025-10-06 209 asm volatile("movl %%es, %%eax" : "=a"(ctxt->es));
94212d34618c26 Mukesh Rathor 2025-10-06 210 asm volatile("movl %%fs, %%eax" : "=a"(ctxt->fs));
94212d34618c26 Mukesh Rathor 2025-10-06 211 asm volatile("movl %%gs, %%eax" : "=a"(ctxt->gs));
94212d34618c26 Mukesh Rathor 2025-10-06 212
94212d34618c26 Mukesh Rathor 2025-10-06 213 native_store_gdt(&ctxt->gdtr);
94212d34618c26 Mukesh Rathor 2025-10-06 214 store_idt(&ctxt->idtr);
94212d34618c26 Mukesh Rathor 2025-10-06 215
94212d34618c26 Mukesh Rathor 2025-10-06 @216 ctxt->gsbase = __rdmsr(MSR_GS_BASE);
94212d34618c26 Mukesh Rathor 2025-10-06 217 ctxt->efer = __rdmsr(MSR_EFER);
94212d34618c26 Mukesh Rathor 2025-10-06 218 ctxt->pat = __rdmsr(MSR_IA32_CR_PAT);
94212d34618c26 Mukesh Rathor 2025-10-06 219 }
94212d34618c26 Mukesh Rathor 2025-10-06 220
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On 18.02.26 16:12, kernel test robot wrote: > Hi Juergen, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on linus/master] > [also build test ERROR on v6.19 next-20260218] > [cannot apply to tip/x86/core kvm/queue kvm/next kvm/linux-next tip/x86/tdx] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Juergen-Gross/x86-alternative-Support-alt_replace_call-with-instructions-after-call/20260218-163031 > base: linus/master > patch link: https://lore.kernel.org/r/20260218082133.400602-11-jgross%40suse.com > patch subject: [PATCH v3 10/16] x86/msr: Use the alternatives mechanism for RDMSR > config: x86_64-randconfig-076-20260218 (https://download.01.org/0day-ci/archive/20260218/202602182222.WEBLSQRj-lkp@intel.com/config) > compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260218/202602182222.WEBLSQRj-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202602182222.WEBLSQRj-lkp@intel.com/ Will add a new patch fixing this. Juergen
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