[PATCH v5 01/16] dt-bindings: Add vendor prefix for Frontgrade Gaisler AB

Arun Muthusamy posted 16 patches 1 month, 2 weeks ago
There is a newer version of this series
[PATCH v5 01/16] dt-bindings: Add vendor prefix for Frontgrade Gaisler AB
Posted by Arun Muthusamy 1 month, 2 weeks ago
From: Ludwig Rydberg <ludwig.rydberg@gaisler.com>

Frontgrade Gaisler AB provides IP cores and supporting development tools
for embedded processors based on the SPARC and RISC-V architectures.
Some essential products are the LEON and NOEL synthesizable processor
models together with a complete development environment and a library of
IP cores (GRLIB).

The company specializes in digital hardware design (ASIC/FPGA) for both
commercial and aerospace applications.

Web site: https://www.gaisler.com/

Signed-off-by: Arun Muthusamy <arun.muthusamy@gaisler.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Ludwig Rydberg <ludwig.rydberg@gaisler.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 424aa7b911a7..4e1b4eeff9ff 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -594,6 +594,8 @@ patternProperties:
     description: Fujitsu Ltd.
   "^fxtec,.*":
     description: FX Technology Ltd.
+  "^gaisler,.*":
+    description: Frontgrade Gaisler AB
   "^galaxycore,.*":
     description: GalaxyCore Inc.
   "^gameforce,.*":
-- 
2.51.0
Re: [PATCH v5 01/16] dt-bindings: Add vendor prefix for Frontgrade Gaisler AB
Posted by Krzysztof Kozlowski 1 month, 2 weeks ago
On 16/02/2026 14:53, Arun Muthusamy wrote:
> From: Ludwig Rydberg <ludwig.rydberg@gaisler.com>
> 
> Frontgrade Gaisler AB provides IP cores and supporting development tools
> for embedded processors based on the SPARC and RISC-V architectures.
> Some essential products are the LEON and NOEL synthesizable processor
> models together with a complete development environment and a library of
> IP cores (GRLIB).
> 
> The company specializes in digital hardware design (ASIC/FPGA) for both
> commercial and aerospace applications.
> 
> Web site: https://www.gaisler.com/
> 
> Signed-off-by: Arun Muthusamy <arun.muthusamy@gaisler.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Ludwig Rydberg <ludwig.rydberg@gaisler.com>

Incorrect DCO chain.

How did it even happen? Look at your previous patches and do not
introduce some random changes.

Best regards,
Krzysztof