Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
has three downstream ports.Two embedded Ethernet devices are present
on one of the downstream ports. All the ports present in the
node represent the downstream ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, which
are on by default and are added as fixed regulators. TC9563 can be
configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 145 +++++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 619a42b5ef48..0fb89e71bf7f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -5,9 +5,45 @@
/dts-v1/;
/plugin/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+&{/} {
+
+ vreg_0p9: regulator-vreg-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_0P9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vreg_dc_12v>;
+ };
+
+ vreg_1p8: regulator-vreg-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_1P8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vreg_dc_12v>;
+ };
+
+ vreg_dc_12v: regulator-vreg-dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "VREG_DC_12V";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
&spi11 {
#address-cells = <1>;
#size-cells = <0>;
@@ -19,3 +55,112 @@ st33htpm0: tpm@0 {
spi-max-frequency = <20000000>;
};
};
+
+&pcie0 {
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>,
+ <0x208 &apps_smmu 0x1c04 0x1>,
+ <0x210 &apps_smmu 0x1c05 0x1>,
+ <0x218 &apps_smmu 0x1c06 0x1>,
+ <0x300 &apps_smmu 0x1c07 0x1>,
+ <0x400 &apps_smmu 0x1c08 0x1>,
+ <0x500 &apps_smmu 0x1c09 0x1>,
+ <0x501 &apps_smmu 0x1c10 0x1>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
+&pcie0_port {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vreg_0p9>;
+ vdd18-supply = <&vreg_1p8>;
+ vdd09-supply = <&vreg_0p9>;
+ vddio1-supply = <&vreg_1p8>;
+ vddio2-supply = <&vreg_1p8>;
+ vddio18-supply = <&vreg_1p8>;
+
+ i2c-parent = <&i2c1 0x77>;
+
+ resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+
+ };
+};
+
+&tlmm {
+ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
+ pins = "gpio78";
+ function = "gpio";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+};
--
2.25.1On Thu, Feb 12, 2026 at 04:14:01PM +0530, Sushrut Shree Trivedi wrote: > Add a node for the TC9563 PCIe switch connected to PCIe0. The switch > has three downstream ports.Two embedded Ethernet devices are present > on one of the downstream ports. All the ports present in the > node represent the downstream ports and embedded endpoints. > > Power to the TC9563 is supplied through two LDO regulators, which > are on by default and are added as fixed regulators. TC9563 can be > configured through I2C. > > Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> > --- > .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 145 +++++++++++++++++++++ > 1 file changed, 145 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote:
> Add a node for the TC9563 PCIe switch connected to PCIe0. The switch
> has three downstream ports.Two embedded Ethernet devices are present
> on one of the downstream ports. All the ports present in the
> node represent the downstream ports and embedded endpoints.
>
> Power to the TC9563 is supplied through two LDO regulators, which
> are on by default and are added as fixed regulators. TC9563 can be
> configured through I2C.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
[...]
> +
> +&tlmm {
> + pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
> + pins = "gpio78";
> + function = "gpio";
> +
> + bias-disable;
In case you're going to respin, please drop the blank line in both patches
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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