[v1] drm/amdgpu: Add HAINAN clock adjustment

[PATCH] drm/amdgpu: Add HAINAN clock adjustment

Posted by decce6 2 months ago

This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from
850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This
patch is for amdgpu.

Signed-off-by: decce6 <decce6@proton.me>
---
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 1f539cc65f41..b5d895537477 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -3468,6 +3468,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
 			max_sclk = 60000;
 			max_mclk = 80000;
 		}
+		if ((adev->pdev->device == 0x666f) &&
+		    (adev->pdev->revision == 0x00)) {
+			max_sclk = 80000;
+			max_mclk = 95000;
+		}
 	} else if (adev->asic_type == CHIP_OLAND) {
 		if ((adev->pdev->revision == 0xC7) ||
 		    (adev->pdev->revision == 0x80) ||
-- 
2.43.0

Re: [PATCH] drm/amdgpu: Add HAINAN clock adjustment

Posted by Alex Deucher 2 months ago

Applied both patches.  Thanks!

Alex

On Tue, Feb 10, 2026 at 3:20 AM decce6 <decce6@proton.me> wrote:
>
> This patch limits the clock speeds of the AMD Radeon R5 M420 GPU from
> 850/1000MHz (core/memory) to 800/950 MHz, making it work stably. This
> patch is for amdgpu.
>
> Signed-off-by: decce6 <decce6@proton.me>
> ---
>  drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index 1f539cc65f41..b5d895537477 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -3468,6 +3468,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
>                         max_sclk = 60000;
>                         max_mclk = 80000;
>                 }
> +               if ((adev->pdev->device == 0x666f) &&
> +                   (adev->pdev->revision == 0x00)) {
> +                       max_sclk = 80000;
> +                       max_mclk = 95000;
> +               }
>         } else if (adev->asic_type == CHIP_OLAND) {
>                 if ((adev->pdev->revision == 0xC7) ||
>                     (adev->pdev->revision == 0x80) ||
> --
> 2.43.0
>
>