[v2] Add RZ/G3L IRQC support

[PATCH v2 0/9] Add RZ/G3L IRQC support

Biju posted 9 patches 4 days, 6 hours ago

Diff against v1 v3
Download series mbox

There is a newer version of this series

.../renesas,rzg2l-irqc.yaml                   | 156 +++++--------
arch/arm64/boot/dts/renesas/r9a08g046.dtsi    |  91 ++++++++
drivers/irqchip/irq-renesas-rzg2l.c           | 218 +++++++++++++++---
3 files changed, 336 insertions(+), 129 deletions(-)

Expand all Fold all

[PATCH v2 0/9] Add RZ/G3L IRQC support

Posted by Biju 4 days, 6 hours ago

From: Biju Das <biju.das.jz@bp.renesas.com>

The IRQC block on RZ/G3L SoC is almost identical to one found on the
RZ/G3S SoC with the difference like it support more External IRQs, GPT
Error Interrupts and also has additional registers for GPT/MTU IRQ
selection, shared IRQ selection between external IRQ and TINT.

It has 16 external interrupts of which 8 interrupts are shared with
TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
selection is based on a register in the ICU block.

v1->v2:
 * Simplified the binding by using pattern for intterrupt-names
 * Fixed the binding warnings reported by bot.

Biju Das (9):
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for
    interrupt-names
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L
    SoC
  irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct
    rzg2l_irqc_priv
  irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
  irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
  irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
  irqchip/renesas-rzg2l: Add RZ/G3L support
  irqchip/renesas-rzg2l: Add shared irq support
  arm64: dts: renesas: r9a08g046: Add ICU node

 .../renesas,rzg2l-irqc.yaml                   | 156 +++++--------
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    |  91 ++++++++
 drivers/irqchip/irq-renesas-rzg2l.c           | 218 +++++++++++++++---
 3 files changed, 336 insertions(+), 129 deletions(-)

-- 
2.43.0