On Wed, Feb 04, 2026 at 11:54:35PM +0900, Koichiro Den wrote:
> Some DesignWare PCIe controllers integrate an eDMA block whose registers
> are located in a dedicated register window. Endpoint function drivers
> may need the physical base and size of this window to map/expose it to a
> peer.
>
> Record the physical base and size of the integrated eDMA register window
> in struct dw_pcie.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/pci/controller/dwc/pcie-designware.c | 4 ++++
> drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 18331d9e85be..d97ad9d2aa9b 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
> pci->edma.reg_base = devm_ioremap_resource(pci->dev, res);
> if (IS_ERR(pci->edma.reg_base))
> return PTR_ERR(pci->edma.reg_base);
> + pci->edma_reg_phys = res->start;
> + pci->edma_reg_size = resource_size(res);
> } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {
> pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;
> + pci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;
> + pci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;
> }
> }
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 43d7606bc987..88e4a9e514e8 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -542,6 +542,8 @@ struct dw_pcie {
> int max_link_speed;
> u8 n_fts[2];
> struct dw_edma_chip edma;
> + phys_addr_t edma_reg_phys;
> + resource_size_t edma_reg_size;
> bool l1ss_support; /* L1 PM Substates support */
> struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
> struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS];
> --
> 2.51.0
>