The M.2 connector on the i.MX8MP EVK can support both PCIe and SDIO
modes. The existing regulator node reg_pcie0 is used to control the
pin56 W_DISABLE1 on the M.2 connector, which is also required by
SDIO-based WLAN modules.

To prepare for adding M.2 SDIO WiFi support, rename the regulator node
from reg_pcie0 to reg_m2_wlan and update its pinctrl and regulator
name accordingly. This allows the same GPIO-controlled power rail to be
reused for both PCIe and SDIO WLAN cards.

No functional behavior changes other than the rename.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 22 ++++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index a1269c7a6cc2..f86d6b428a47 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -134,11 +134,11 @@ reg_audio_pwr: regulator-audio-pwr {
 		enable-active-high;
 	};
 
-	reg_pcie0: regulator-pcie {
+	reg_m2_wlan: regulator-wlan {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pcie0_reg>;
-		regulator-name = "MPCIE_3V3";
+		pinctrl-0 = <&pinctrl_reg_wlan>;
+		regulator-name = "WLAN_EN";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
@@ -764,8 +764,8 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	/* This property is deprecated, use reset-gpios from the Root Port node. */
 	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
-	vpcie-supply = <&reg_pcie0>;
-	vpcie3v3aux-supply = <&reg_pcie0>;
+	vpcie-supply = <&reg_m2_wlan>;
+	vpcie3v3aux-supply = <&reg_m2_wlan>;
 	supports-clkreq;
 	status = "okay";
 };
@@ -1067,12 +1067,6 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
 		>;
 	};
 
-	pinctrl_pcie0_reg: pcie0reggrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
-		>;
-	};
-
 	pinctrl_pdm: pdmgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6
@@ -1119,6 +1113,12 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
+	pinctrl_reg_wlan: regwlangrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
-- 
2.37.1

On Wed, Feb 04, 2026 at 10:32:03AM +0800, Sherry Sun wrote:
> The M.2 connector on the i.MX8MP EVK can support both PCIe and SDIO
> modes. The existing regulator node reg_pcie0 is used to control the
> pin56 W_DISABLE1 on the M.2 connector, which is also required by
> SDIO-based WLAN modules.
>
> To prepare for adding M.2 SDIO WiFi support, rename the regulator node
> from reg_pcie0 to reg_m2_wlan and update its pinctrl and regulator
> name accordingly. This allows the same GPIO-controlled power rail to be
> reused for both PCIe and SDIO WLAN cards.
>
> No functional behavior changes other than the rename.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 22 ++++++++++----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index a1269c7a6cc2..f86d6b428a47 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -134,11 +134,11 @@ reg_audio_pwr: regulator-audio-pwr {
>  		enable-active-high;
>  	};
>
> -	reg_pcie0: regulator-pcie {
> +	reg_m2_wlan: regulator-wlan {

Needn't complex rename, just add second label

reg_m2_wlan: reg_pcie0: regulator-pcie {

Frank

>  		compatible = "regulator-fixed";
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_pcie0_reg>;
> -		regulator-name = "MPCIE_3V3";
> +		pinctrl-0 = <&pinctrl_reg_wlan>;
> +		regulator-name = "WLAN_EN";
>  		regulator-min-microvolt = <3300000>;
>  		regulator-max-microvolt = <3300000>;
>  		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> @@ -764,8 +764,8 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	/* This property is deprecated, use reset-gpios from the Root Port node. */
>  	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> -	vpcie-supply = <&reg_pcie0>;
> -	vpcie3v3aux-supply = <&reg_pcie0>;
> +	vpcie-supply = <&reg_m2_wlan>;
> +	vpcie3v3aux-supply = <&reg_m2_wlan>;
>  	supports-clkreq;
>  	status = "okay";
>  };
> @@ -1067,12 +1067,6 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
>  		>;
>  	};
>
> -	pinctrl_pcie0_reg: pcie0reggrp {
> -		fsl,pins = <
> -			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
> -		>;
> -	};
> -
>  	pinctrl_pdm: pdmgrp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6
> @@ -1119,6 +1113,12 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
>  		>;
>  	};
>
> +	pinctrl_reg_wlan: regwlangrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
> +		>;
> +	};
> +
>  	pinctrl_uart1: uart1grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
> --
> 2.37.1
>