To configure the video PLLs and enable the video GDSCs on SM8250,
platform, the MX rail must be ON along with MMCX. Split the bindings
file in order to provide separate file utilizing MMCX and MX power
domains.
Fixes: dafb992a95e1 ("dt-bindings: clock: add SM8250 QCOM video clock bindings")
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8250-videocc.yaml | 85 ++++++++++++++++++++++
.../devicetree/bindings/clock/qcom,videocc.yaml | 20 -----
2 files changed, 85 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.yaml
new file mode 100644
index 000000000000..341d3cbb7cbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-videocc.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8250-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller
+
+maintainers:
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm video clock control module provides the clocks, resets and power
+ domains on Qualcomm SoCs.
+
+ See also::
+ include/dt-bindings/clock/qcom,videocc-sm8250.h
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - qcom,sm8250-videocc
+
+ clocks:
+ items:
+ - description: AHB
+ - description: Board XO source
+ - description: Board active XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+
+ power-domains:
+ items:
+ - description:
+ A phandle and PM domain specifier for the MMCX power domain.
+ - description:
+ A phandle and PM domain specifier for the MX power domain.
+
+ required-opps:
+ items:
+ - description:
+ A phandle to an OPP node describing required MMCX performance point.
+ - description:
+ A phandle to an OPP node describing required MX performance point.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#power-domain-cells'
+ - power-domains
+ - required-opps
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@ab00000 {
+ compatible = "qcom,sm8250-videocc";
+ reg = <0x0ab00000 0x10000>;
+ clocks = <&gcc_gcc_video_ahb_clk>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "iface",
+ "bi_tcxo",
+ "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MX>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index f4ff9acef9d5..8676c7e22b4c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -19,7 +19,6 @@ description: |
include/dt-bindings/clock/qcom,videocc-sc7280.h
include/dt-bindings/clock/qcom,videocc-sdm845.h
include/dt-bindings/clock/qcom,videocc-sm8150.h
- include/dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:
@@ -30,7 +29,6 @@ properties:
- qcom,sdm845-videocc
- qcom,sm6350-videocc
- qcom,sm8150-videocc
- - qcom,sm8250-videocc
- items:
- const: qcom,sc8180x-videocc
- const: qcom,sm8150-videocc
@@ -128,24 +126,6 @@ allOf:
- const: iface
- const: bi_tcxo
- - if:
- properties:
- compatible:
- enum:
- - qcom,sm8250-videocc
- then:
- properties:
- clocks:
- items:
- - description: AHB
- - description: Board XO source
- - description: Board active XO source
- clock-names:
- items:
- - const: iface
- - const: bi_tcxo
- - const: bi_tcxo_ao
-
unevaluatedProperties: false
examples:
--
2.47.3On Wed, Feb 04, 2026 at 02:59:49AM +0200, Dmitry Baryshkov wrote: > To configure the video PLLs and enable the video GDSCs on SM8250, > platform, the MX rail must be ON along with MMCX. Split the bindings > file in order to provide separate file utilizing MMCX and MX power > domains. ... > + > +description: | > + Qualcomm video clock control module provides the clocks, resets and power > + domains on Qualcomm SoCs. > + > + See also:: Only one ':', please. It was a mistake to introduce :: > + clock-names: > + items: > + - const: iface > + - const: bi_tcxo > + - const: bi_tcxo_ao > + > + power-domains: > + items: > + - description: > + A phandle and PM domain specifier for the MMCX power domain. > + - description: > + A phandle and PM domain specifier for the MX power domain. This is an ABI break, so please say in the commit what was not working or why this ABI break is really justified. Currently you just give a hint that it is needed for PLL configuration, but honestly - why would we care to configure PLL if everything was working correct before? Best regards, Krzysztof
On Thu, Feb 05, 2026 at 12:31:54PM +0100, Krzysztof Kozlowski wrote: > On Wed, Feb 04, 2026 at 02:59:49AM +0200, Dmitry Baryshkov wrote: > > To configure the video PLLs and enable the video GDSCs on SM8250, > > platform, the MX rail must be ON along with MMCX. Split the bindings > > file in order to provide separate file utilizing MMCX and MX power > > domains. > > ... > > > + > > +description: | > > + Qualcomm video clock control module provides the clocks, resets and power > > + domains on Qualcomm SoCs. > > + > > + See also:: > > Only one ':', please. It was a mistake to introduce :: Ack. > > > + clock-names: > > + items: > > + - const: iface > > + - const: bi_tcxo > > + - const: bi_tcxo_ao > > + > > + power-domains: > > + items: > > + - description: > > + A phandle and PM domain specifier for the MMCX power domain. > > + - description: > > + A phandle and PM domain specifier for the MX power domain. > > This is an ABI break, so please say in the commit what was not working > or why this ABI break is really justified. Currently you just give a > hint that it is needed for PLL configuration, but honestly - why would > we care to configure PLL if everything was working correct before? I must admit, I c&p'ed the commit message from [1] which was ack'ed by Rob and accepted into the kernel. What is the difference? [1] https://lore.kernel.org/all/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com/ -- With best wishes Dmitry
On 05/02/2026 13:48, Dmitry Baryshkov wrote: >> >>> + clock-names: >>> + items: >>> + - const: iface >>> + - const: bi_tcxo >>> + - const: bi_tcxo_ao >>> + >>> + power-domains: >>> + items: >>> + - description: >>> + A phandle and PM domain specifier for the MMCX power domain. >>> + - description: >>> + A phandle and PM domain specifier for the MX power domain. >> >> This is an ABI break, so please say in the commit what was not working >> or why this ABI break is really justified. Currently you just give a >> hint that it is needed for PLL configuration, but honestly - why would >> we care to configure PLL if everything was working correct before? > > I must admit, I c&p'ed the commit message from [1] which was ack'ed by > Rob and accepted into the kernel. What is the difference? No difference. To me both are insufficiently explained as fixes, but other maintainer might have different opinion. I don't mind that. > > [1] https://lore.kernel.org/all/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com/ > Best regards, Krzysztof
On 2/5/26 12:31 PM, Krzysztof Kozlowski wrote: > On Wed, Feb 04, 2026 at 02:59:49AM +0200, Dmitry Baryshkov wrote: >> To configure the video PLLs and enable the video GDSCs on SM8250, >> platform, the MX rail must be ON along with MMCX. Split the bindings >> file in order to provide separate file utilizing MMCX and MX power >> domains. > > ... > >> + >> +description: | >> + Qualcomm video clock control module provides the clocks, resets and power >> + domains on Qualcomm SoCs. >> + >> + See also:: > > Only one ':', please. It was a mistake to introduce :: > >> + clock-names: >> + items: >> + - const: iface >> + - const: bi_tcxo >> + - const: bi_tcxo_ao >> + >> + power-domains: >> + items: >> + - description: >> + A phandle and PM domain specifier for the MMCX power domain. >> + - description: >> + A phandle and PM domain specifier for the MX power domain. > > This is an ABI break, so please say in the commit what was not working > or why this ABI break is really justified. Currently you just give a > hint that it is needed for PLL configuration, but honestly - why would > we care to configure PLL if everything was working correct before? I fully expect it to kaboom if you turn off the display (which also holds a high vote on MMCX) Konrad
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