Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
in cascade to the first TC9563 switch via the former's downstream port.
Two embedded Ethernet devices are present on one of the downstream
ports of this second switch as well. All the ports present in the
node represent the downstream ports and embedded endpoints.
The second TC9563 is powered up via the same LDO regulators as the first
one, and these can be controlled via two GPIOs, which are already present
as fixed regulators. This TC9563 can also be configured through I2C.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
.../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 96 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +--
2 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 89bbcab0908d..1744c9c8bd50 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -146,6 +146,91 @@ pcie0_switch0_eth1: pci@0,1 {
};
};
+&pcie1 {
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>,
+ <0x208 &apps_smmu 0x1c84 0x1>,
+ <0x210 &apps_smmu 0x1c85 0x1>,
+ <0x218 &apps_smmu 0x1c86 0x1>,
+ <0x300 &apps_smmu 0x1c87 0x1>,
+ <0x408 &apps_smmu 0x1c90 0x1>,
+ <0x410 &apps_smmu 0x1c91 0x1>,
+ <0x418 &apps_smmu 0x1c92 0x1>,
+ <0x500 &apps_smmu 0x1c93 0x1>,
+ <0x600 &apps_smmu 0x1c94 0x1>,
+ <0x700 &apps_smmu 0x1c95 0x1>,
+ <0x701 &apps_smmu 0x1c96 0x1>,
+ <0x800 &apps_smmu 0x1c97 0x1>,
+ <0x900 &apps_smmu 0x1c98 0x1>,
+ <0x901 &apps_smmu 0x1c99 0x1>;
+};
+
+&pcie1_switch0_dsp1 {
+ pcie1_switch1_usp: pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x30000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c1 0x33>;
+
+ resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_tc9563_resx_n>;
+ pinctrl-names = "default";
+
+ pcie1_switch1_dsp1: pcie@1,0 {
+ reg = <0x40800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie1_switch1_dsp2: pcie@2,0 {
+ reg = <0x41000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie1_switch1_dsp3: pcie@3,0 {
+ reg = <0x41800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+
+ pcie1_switch1_eth0: pci@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie1_switch1_eth1: pci@0,1 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&tlmm {
pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
pins = "gpio78";
@@ -156,4 +241,15 @@ pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
output-enable;
power-source = <0>;
};
+
+ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
+ pins = "gpio124";
+ function = "gpio";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+
};
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e3d2f01881ae..ffe4521eb289 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -828,7 +828,7 @@ &pcie1_phy {
};
&pcie1_port0 {
- pcie@0,0 {
+ pcie1_switch0_usp: pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
@@ -852,7 +852,7 @@ pcie@0,0 {
pinctrl-0 = <&tc9563_resx_n>;
pinctrl-names = "default";
- pcie@1,0 {
+ pcie1_switch0_dsp1: pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -862,7 +862,7 @@ pcie@1,0 {
bus-range = <0x3 0xff>;
};
- pcie@2,0 {
+ pcie1_switch0_dsp2: pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -872,7 +872,7 @@ pcie@2,0 {
bus-range = <0x4 0xff>;
};
- pcie@3,0 {
+ pcie1_switch0_dsp3: pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -880,7 +880,7 @@ pcie@3,0 {
ranges;
bus-range = <0x5 0xff>;
- pci@0,0 {
+ pcie1_switch0_eth0: pci@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
@@ -888,7 +888,7 @@ pci@0,0 {
ranges;
};
- pci@0,1 {
+ pcie1_switch0_eth1: pci@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
--
2.25.1On 2/3/26 5:31 AM, Sushrut Shree Trivedi wrote:
> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
> in cascade to the first TC9563 switch via the former's downstream port.
>
> Two embedded Ethernet devices are present on one of the downstream
> ports of this second switch as well. All the ports present in the
> node represent the downstream ports and embedded endpoints.
>
> The second TC9563 is powered up via the same LDO regulators as the first
> one, and these can be controlled via two GPIOs, which are already present
> as fixed regulators. This TC9563 can also be configured through I2C.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
> ---
> .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 96 ++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +--
> 2 files changed, 102 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> index 89bbcab0908d..1744c9c8bd50 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> @@ -146,6 +146,91 @@ pcie0_switch0_eth1: pci@0,1 {
> };
> };
>
> +&pcie1 {
> + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> + <0x100 &apps_smmu 0x1c81 0x1>,
Please set your tab width to 8 and align the '<'s
[...]
> +&pcie1_switch0_dsp1 {
> + pcie1_switch1_usp: pcie@0,0 {
This label is unused
[...]
> + pcie1_switch1_dsp1: pcie@1,0 {
> + reg = <0x40800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + };
> +
> + pcie1_switch1_dsp2: pcie@2,0 {
> + reg = <0x41000 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + device_type = "pci";
> + ranges;
> + };
> +
> + pcie1_switch1_dsp3: pcie@3,0 {
And so are all three of these
> + reg = <0x41800 0x0 0x0 0x0 0x0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> +
> + pcie1_switch1_eth0: pci@0,0 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges;
> + };
> +
> + pcie1_switch1_eth1: pci@0,1 {
These two are unused as well
[...]
> + pcie1_switch0_dsp1: pcie@1,0 {
This one is in use
> reg = <0x20800 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -862,7 +862,7 @@ pcie@1,0 {
> bus-range = <0x3 0xff>;
> };
>
> - pcie@2,0 {
> + pcie1_switch0_dsp2: pcie@2,0 {
> reg = <0x21000 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -872,7 +872,7 @@ pcie@2,0 {
> bus-range = <0x4 0xff>;
> };
>
> - pcie@3,0 {
> + pcie1_switch0_dsp3: pcie@3,0 {
But these two aren't. Plus the DSP3 seems to be hardwired to eth
so it seems like that won't ever change. DSP2 will understandably
be useful, since any derivative of this mezz could attach more
devices
> reg = <0x21800 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -880,7 +880,7 @@ pcie@3,0 {
> ranges;
> bus-range = <0x5 0xff>;
>
> - pci@0,0 {
> + pcie1_switch0_eth0: pci@0,0 {
> reg = <0x50000 0x0 0x0 0x0 0x0>;
> #address-cells = <3>;
> #size-cells = <2>;
> @@ -888,7 +888,7 @@ pci@0,0 {
> ranges;
> };
>
> - pci@0,1 {
> + pcie1_switch0_eth1: pci@0,1 {
These two are again unused
Konrad
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