drivers/iommu/intel/pasid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
The PASID_FLAG_PAGE_SNOOP and PASID_FLAG_PWSNP constants are identical.
This will cause the pasid code to always set both or neither of the
PGSNP and PWSNP bits in PASID table entries. However, PWSNP is a
reserved bit if SMPWC is not set in the IOMMU's extended capability
register, even if SC is supported.
This has resulted in DMAR errors when testing the iommufd code on an
Arrow Lake platform. With this patch, those errors disappear and the
PASID table entries look correct.
Fixes: 101a2854110fa ("iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry")
Signed-off-by: Viktor Kleen <viktor@kleen.org>
---
drivers/iommu/intel/pasid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index b4c85242dc79..3809793e0259 100644
--- a/drivers/iommu/intel/pasid.h
+++ b/drivers/iommu/intel/pasid.h
@@ -24,7 +24,7 @@
#define PASID_FLAG_NESTED BIT(1)
#define PASID_FLAG_PAGE_SNOOP BIT(2)
-#define PASID_FLAG_PWSNP BIT(2)
+#define PASID_FLAG_PWSNP BIT(3)
/*
* The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
--
2.51.0
On 2/3/26 03:21, Viktor Kleen wrote:
> The PASID_FLAG_PAGE_SNOOP and PASID_FLAG_PWSNP constants are identical.
> This will cause the pasid code to always set both or neither of the
> PGSNP and PWSNP bits in PASID table entries. However, PWSNP is a
> reserved bit if SMPWC is not set in the IOMMU's extended capability
> register, even if SC is supported.
>
> This has resulted in DMAR errors when testing the iommufd code on an
> Arrow Lake platform. With this patch, those errors disappear and the
> PASID table entries look correct.
>
> Fixes: 101a2854110fa ("iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry")
> Signed-off-by: Viktor Kleen<viktor@kleen.org>
> ---
> drivers/iommu/intel/pasid.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Queued for iommu/vt-d.
Thanks,
baolu
On Mon, Feb 02, 2026 at 07:21:05PM +0000, Viktor Kleen wrote:
> The PASID_FLAG_PAGE_SNOOP and PASID_FLAG_PWSNP constants are identical.
> This will cause the pasid code to always set both or neither of the
> PGSNP and PWSNP bits in PASID table entries. However, PWSNP is a
> reserved bit if SMPWC is not set in the IOMMU's extended capability
> register, even if SC is supported.
>
> This has resulted in DMAR errors when testing the iommufd code on an
> Arrow Lake platform. With this patch, those errors disappear and the
> PASID table entries look correct.
>
> Fixes: 101a2854110fa ("iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry")
> Signed-off-by: Viktor Kleen <viktor@kleen.org>
> ---
> drivers/iommu/intel/pasid.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
It looks like a typo to me too
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
It should also be:
Cc: stable@vger.kernel.org
Jason
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