The MSI-X configuration code reads from the correct physical function's
register space using dw_pcie_ep_readw_dbi(), but writes back only to
PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
MSI-X configuration for other PFs.
Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
register space, matching the read operation.
Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
Signed-off-by: Aksh Garg <a-garg7@ti.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7e7844ff0f7e..771241e1a2c9 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
val &= ~PCI_MSIX_FLAGS_QSIZE;
val |= nr_irqs - 1; /* encoded as N-1 */
- dw_pcie_writew_dbi(pci, reg, val);
+ dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
reg = ep_func->msix_cap + PCI_MSIX_TABLE;
val = offset | bir;
--
2.34.1
On Mon, Feb 02, 2026 at 12:57:57PM +0530, Aksh Garg wrote:
> The MSI-X configuration code reads from the correct physical function's
> register space using dw_pcie_ep_readw_dbi(), but writes back only to
> PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
> MSI-X configuration for other PFs.
>
> Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
> register space, matching the read operation.
>
> Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
> Signed-off-by: Aksh Garg <a-garg7@ti.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e7844ff0f7e..771241e1a2c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> val &= ~PCI_MSIX_FLAGS_QSIZE;
> val |= nr_irqs - 1; /* encoded as N-1 */
> - dw_pcie_writew_dbi(pci, reg, val);
> + dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
>
> reg = ep_func->msix_cap + PCI_MSIX_TABLE;
> val = offset | bir;
> --
> 2.34.1
>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
However, please also fix the only remaining place in this file which still
uses the incorrect dw_pcie_writew_dbi() instead of dw_pcie_ep_writew_dbi()
i.e.:
dw_pcie_ep_raise_msix_irq_doorbell().
On Mon, Feb 02, 2026 at 08:55:52AM +0100, Niklas Cassel wrote:
> On Mon, Feb 02, 2026 at 12:57:57PM +0530, Aksh Garg wrote:
> > The MSI-X configuration code reads from the correct physical function's
> > register space using dw_pcie_ep_readw_dbi(), but writes back only to
> > PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
> > MSI-X configuration for other PFs.
> >
> > Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
> > register space, matching the read operation.
> >
> > Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
> > Signed-off-by: Aksh Garg <a-garg7@ti.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 7e7844ff0f7e..771241e1a2c9 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> > val &= ~PCI_MSIX_FLAGS_QSIZE;
> > val |= nr_irqs - 1; /* encoded as N-1 */
> > - dw_pcie_writew_dbi(pci, reg, val);
> > + dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
> >
> > reg = ep_func->msix_cap + PCI_MSIX_TABLE;
> > val = offset | bir;
> > --
> > 2.34.1
> >
>
> Reviewed-by: Niklas Cassel <cassel@kernel.org>
>
>
> However, please also fix the only remaining place in this file which still
> uses the incorrect dw_pcie_writew_dbi() instead of dw_pcie_ep_writew_dbi()
>
> i.e.:
> dw_pcie_ep_raise_msix_irq_doorbell().
Perhaps doorbell is special, and there is only one register for this...
But then, perhaps add a comment why this is the only place that needs
to not supply func_no.
On 02/02/26 13:27, Niklas Cassel wrote:
> On Mon, Feb 02, 2026 at 08:55:52AM +0100, Niklas Cassel wrote:
>> On Mon, Feb 02, 2026 at 12:57:57PM +0530, Aksh Garg wrote:
>> > The MSI-X configuration code reads from the correct physical function's
>> > register space using dw_pcie_ep_readw_dbi(), but writes back only to
>> > PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
>> > MSI-X configuration for other PFs.
>> >
>> > Fix this by using dw_pcie_ep_writew_dbi() to write to the correct PF's
>> > register space, matching the read operation.
>> >
>> > Fixes: 70fa02ca1446 ("PCI: dwc: Add dw_pcie_ep_{read,write}_dbi[2] helpers")
>> > Signed-off-by: Aksh Garg <a-garg7@ti.com>
>> > ---
>> > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
>> > index 7e7844ff0f7e..771241e1a2c9 100644
>> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
>> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
>> > @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>> > val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
>> > val &= ~PCI_MSIX_FLAGS_QSIZE;
>> > val |= nr_irqs - 1; /* encoded as N-1 */
>> > - dw_pcie_writew_dbi(pci, reg, val);
>> > + dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
>> >
>> > reg = ep_func->msix_cap + PCI_MSIX_TABLE;
>> > val = offset | bir;
>> > --
>> > 2.34.1
>> >
>>
>> Reviewed-by: Niklas Cassel <cassel@kernel.org>
>>
>>
>> However, please also fix the only remaining place in this file which still
>> uses the incorrect dw_pcie_writew_dbi() instead of dw_pcie_ep_writew_dbi()
>>
>> i.e.:
>> dw_pcie_ep_raise_msix_irq_doorbell().
>
> Perhaps doorbell is special, and there is only one register for this...
>
Yes, we have only one doorbell register.
> But then, perhaps add a comment why this is the only place that needs
> to not supply func_no.
However, I think the offset (0x948) of the register is self-explanatory,
as after 0x700, we have port logic registers, which are per-device, not
per-PF.
>
On Mon, Feb 02, 2026 at 01:45:49PM +0530, Aksh Garg wrote:
> On 02/02/26 13:27, Niklas Cassel wrote:
> > On Mon, Feb 02, 2026 at 08:55:52AM +0100, Niklas Cassel wrote:
> > > On Mon, Feb 02, 2026 at 12:57:57PM +0530, Aksh Garg wrote:
> > > > The MSI-X configuration code reads from the correct physical function's
> > > > register space using dw_pcie_ep_readw_dbi(), but writes back only to
> > > > PF0 using the old dw_pcie_writew_dbi() helper. This causes incorrect
> > > > MSI-X configuration for other PFs.
> > > > > Fix this by using dw_pcie_ep_writew_dbi() to write to the
> > > correct PF's
> > > > register space, matching the read operation.
> > > > > Fixes: 70fa02ca1446 ("PCI: dwc: Add
> > > dw_pcie_ep_{read,write}_dbi[2] helpers")
> > > > Signed-off-by: Aksh Garg <a-garg7@ti.com>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > index 7e7844ff0f7e..771241e1a2c9 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > @@ -745,7 +745,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > > val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> > > > val &= ~PCI_MSIX_FLAGS_QSIZE;
> > > > val |= nr_irqs - 1; /* encoded as N-1 */
> > > > - dw_pcie_writew_dbi(pci, reg, val);
> > > > + dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
> > > > > reg = ep_func->msix_cap + PCI_MSIX_TABLE;
> > > > val = offset | bir;
> > > > -- > 2.34.1
> > > >
> > >
> > > Reviewed-by: Niklas Cassel <cassel@kernel.org>
> > >
> > >
> > > However, please also fix the only remaining place in this file which still
> > > uses the incorrect dw_pcie_writew_dbi() instead of dw_pcie_ep_writew_dbi()
> > >
> > > i.e.:
> > > dw_pcie_ep_raise_msix_irq_doorbell().
> >
> > Perhaps doorbell is special, and there is only one register for this...
> >
>
> Yes, we have only one doorbell register.
>
> > But then, perhaps add a comment why this is the only place that needs
> > to not supply func_no.
>
> However, I think the offset (0x948) of the register is self-explanatory,
> as after 0x700, we have port logic registers, which are per-device, not
> per-PF.
The macro PCIE_MSIX_DOORBELL does kind of hide the offset, and not everyone
who reads the driver might know the that PL registers start at 0x700.
But sure, msg_data which is written to the doorbell was crafted with a func_no
shift, so perhaps it is self explanatory if you look some lines above the
dw_pcie_writel_dbi() which does not supply func_no, so perhaps a comment is
superfluous in this case.
Kind regards,
Niklas
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