Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
Loongson STMMAC use 125MHz clocks and need 62 freq division to within
2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
to 100-150MHz.

Cc: stable@vger.kernel.org
Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 107a7c84ace8..c05e3e7a539c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -91,8 +91,8 @@ static void loongson_default_data(struct pci_dev *pdev,
 	/* Get bus_id, this can be overwritten later */
 	plat->bus_id = pci_dev_id(pdev);
 
-	/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
-	plat->clk_csr = STMMAC_CSR_20_35M;
+	/* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
+	plat->clk_csr = STMMAC_CSR_100_150M;
 	plat->core_type = DWMAC_CORE_GMAC;
 	plat->force_sf_dma_mode = 1;
 
-- 
2.47.3

On Sun, Feb 01, 2026 at 10:37:00AM +0800, Huacai Chen wrote:
> Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
> and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
> Loongson STMMAC use 125MHz clocks and need 62 freq division to within
> 2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
> to 100-150MHz.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

Fixes tag?

Does the error mean that MDC is ticking at 9.7Mhz? That is pretty fast
for PHYs. But i assume it must work for some boards.

Separate to this fix, you might be interested in:

  clock-frequency:
    description:
      Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
      defined 2.5MHz should only be used when all devices on the bus support
      the given clock speed.

So you could allow faster MDC values using this property.

    Andrew

---
pw-bot: cr

Hi, Andrew,

On Tue, Feb 3, 2026 at 5:42 AM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Sun, Feb 01, 2026 at 10:37:00AM +0800, Huacai Chen wrote:
> > Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
> > and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
> > Loongson STMMAC use 125MHz clocks and need 62 freq division to within
> > 2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
> > to 100-150MHz.
> >
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
> > Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>
> Fixes tag?
OK, will add it.

>
> Does the error mean that MDC is ticking at 9.7Mhz? That is pretty fast
> for PHYs. But i assume it must work for some boards.
Yes, some PHYs work while others don't.

Huacai
>
> Separate to this fix, you might be interested in:
>
>   clock-frequency:
>     description:
>       Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
>       defined 2.5MHz should only be used when all devices on the bus support
>       the given clock speed.
>
> So you could allow faster MDC values using this property.
>
>     Andrew
>
> ---
> pw-bot: cr