From: Biju Das <biju.das.jz@bp.renesas.com>
Add GPIO clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index e74bab2df29a..4d1b9c8c524f 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -174,6 +174,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1),
DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1),
DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1),
+ DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1),
};
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
@@ -221,6 +222,8 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
MSTOP(BUS_PERI_COM, BIT(3))),
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
MSTOP(BUS_MCPU2, BIT(1))),
+ DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
+ MSTOP(BUS_PERI_CPU, BIT(6))),
};
static const struct rzg2l_reset r9a08g046_resets[] = {
@@ -232,6 +235,9 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
+ DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
+ DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
};
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
--
2.43.0