The etherenet controller on Spacemit K3 SoC is Synopsys DesignWare
MAC (version 5.40a), with the following special point:
1. The rate of the tx clock line is auto changed when the mac speed
rate is changed, and no need for changing the input tx clock.
2. This controller require a extra syscon device to configure the
interface type, enable wake up interrupt and delay configuration
if needed.
Add Spacemit dwmac driver support on the Spacemit K3 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../ethernet/stmicro/stmmac/dwmac-spacemit.c | 218 ++++++++++++++++++
3 files changed, 231 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 907fe2e927f0..583a4692f5da 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -216,6 +216,18 @@ config DWMAC_SOPHGO
for the stmmac device driver. This driver is used for the
ethernet controllers on various Sophgo SoCs.
+config DWMAC_SPACEMIT
+ tristate "Spacemit dwmac support"
+ depends on OF && (ARCH_SPACEMIT || COMPILE_TEST)
+ select MFD_SYSCON
+ default m if ARCH_SPACEMIT
+ help
+ Support for ethernet controllers on Spacemit RISC-V SoCs
+
+ This selects the Spacemit platform specific glue layer support
+ for the stmmac device driver. This driver is used for the
+ Spacemit K3 ethernet controllers.
+
config DWMAC_STARFIVE
tristate "StarFive dwmac support"
depends on OF && (ARCH_STARFIVE || COMPILE_TEST)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 7bf528731034..9e32045631d8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o
obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o
obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
obj-$(CONFIG_DWMAC_SOPHGO) += dwmac-sophgo.o
+obj-$(CONFIG_DWMAC_SPACEMIT) += dwmac-spacemit.o
obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o
obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
new file mode 100644
index 000000000000..d5cb91182963
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Spacemit DWMAC platform driver
+ *
+ * Copyright (C) 2026 Inochi Amaoto <inochiama@gmail.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/math.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include "stmmac_platform.h"
+
+/* ctrl register bits */
+#define PHY_INTF_RGMII BIT(3)
+#define PHY_INTF_MII BIT(4)
+
+#define WAKE_IRQ_EN BIT(9)
+#define PHY_IRQ_EN BIT(12)
+
+/* dline register bits */
+#define RGMII_RX_DLINE_EN BIT(0)
+#define RGMII_RX_DLINE_STEP GENMASK(5, 4)
+#define RGMII_RX_DLINE_CODE GENMASK(15, 8)
+#define RGMII_TX_DLINE_EN BIT(16)
+#define RGMII_TX_DLINE_STEP GENMASK(21, 20)
+#define RGMII_TX_DLINE_CODE GENMASK(31, 24)
+
+#define MAX_DLINE_DELAY_CODE 0xff
+#define MAX_WORKED_DELAY 2800
+
+/* Note: the delay step value is at 0.1ps */
+static const unsigned int k3_delay_step_10x[4] = {
+ 367, 493, 559, 685
+};
+
+static int spacemit_dwmac_set_delay(struct regmap *apmu,
+ unsigned int dline_offset,
+ unsigned int tx_code, unsigned int tx_config,
+ unsigned int rx_code, unsigned int rx_config)
+{
+ unsigned int mask, val;
+
+ mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN |
+ RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN;
+ val = FIELD_PREP(RGMII_TX_DLINE_STEP, tx_config) |
+ FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN |
+ FIELD_PREP(RGMII_RX_DLINE_STEP, rx_config) |
+ FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN;
+
+ return regmap_update_bits(apmu, dline_offset, mask, val);
+}
+
+static int spacemit_dwmac_detected_delay_value(unsigned int delay,
+ unsigned int *config)
+{
+ unsigned int best_delay = 0;
+ unsigned int best_config = 0;
+ int best_code = 0;
+ int i;
+
+ if (delay == 0)
+ return 0;
+
+ if (delay > MAX_WORKED_DELAY)
+ return -EINVAL;
+
+ /*
+ * Note K3 require a specific factor for calculate
+ * the delay, in this scenario it is 0.9. So the
+ * formula is code * step / 10 * 0.9
+ */
+ for (i = 0; i < ARRAY_SIZE(k3_delay_step_10x); i++) {
+ unsigned int step = k3_delay_step_10x[i];
+ int code = DIV_ROUND_CLOSEST(delay * 10 * 10, step * 9);
+ unsigned int tmp = code * step * 9 / 10 / 10;
+
+ if (abs(tmp - delay) < abs(best_delay - delay)) {
+ best_code = code;
+ best_delay = tmp;
+ best_config = i;
+ }
+ }
+
+ *config = best_config;
+
+ return best_code;
+}
+
+static int spacemit_dwmac_fix_delay(struct plat_stmmacenet_data *plat_dat,
+ struct regmap *apmu,
+ unsigned int dline_offset,
+ unsigned int tx_delay, unsigned int rx_delay)
+{
+ unsigned int rx_config = 0;
+ unsigned int tx_config = 0;
+ int rx_code;
+ int tx_code;
+
+ rx_code = spacemit_dwmac_detected_delay_value(rx_delay, &rx_config);
+ if (rx_code < 0)
+ return rx_code;
+
+ tx_code = spacemit_dwmac_detected_delay_value(tx_delay, &tx_config);
+ if (tx_code < 0)
+ return tx_code;
+
+ return spacemit_dwmac_set_delay(apmu, dline_offset,
+ tx_code, tx_config,
+ rx_code, rx_config);
+}
+
+static int spacemit_dwmac_update_ifconfig(struct plat_stmmacenet_data *plat_dat,
+ struct stmmac_resources *stmmac_res,
+ struct regmap *apmu,
+ unsigned int ctrl_offset)
+{
+ unsigned int mask = PHY_INTF_MII | PHY_INTF_RGMII | WAKE_IRQ_EN;
+ unsigned int val = 0;
+
+ switch (plat_dat->phy_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ val = PHY_INTF_MII;
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val = PHY_INTF_RGMII;
+ break;
+
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ if (stmmac_res->wol_irq >= 0)
+ val |= WAKE_IRQ_EN;
+
+ return regmap_update_bits(apmu, ctrl_offset, mask, val);
+}
+
+static int spacemit_dwmac_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct device *dev = &pdev->dev;
+ unsigned int offset[2];
+ struct regmap *apmu;
+ struct clk *clk_tx;
+ u32 rx_delay = 0;
+ u32 tx_delay = 0;
+ int ret;
+
+ ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to get platform resources\n");
+
+ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return dev_err_probe(dev, PTR_ERR(plat_dat),
+ "failed to parse DT parameters\n");
+
+ clk_tx = devm_clk_get_enabled(&pdev->dev, "tx");
+ if (IS_ERR(clk_tx))
+ return dev_err_probe(&pdev->dev, PTR_ERR(clk_tx),
+ "failed to get tx clock\n");
+
+ apmu = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, "spacemit,apmu", 2, offset);
+ if (IS_ERR(apmu))
+ return dev_err_probe(dev, PTR_ERR(apmu),
+ "Failed to get apmu regmap\n");
+
+ ret = spacemit_dwmac_update_ifconfig(plat_dat, &stmmac_res,
+ apmu, offset[0]);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to configure ifconfig\n");
+
+ of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", &tx_delay);
+ of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", &rx_delay);
+
+ ret = spacemit_dwmac_fix_delay(plat_dat, apmu, offset[1], tx_delay, rx_delay);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to configure delay\n");
+
+ return stmmac_dvr_probe(dev, plat_dat, &stmmac_res);
+}
+
+static const struct of_device_id spacemit_dwmac_match[] = {
+ { .compatible = "spacemit,k3-dwmac" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, spacemit_dwmac_match);
+
+static struct platform_driver spacemit_dwmac_driver = {
+ .probe = spacemit_dwmac_probe,
+ .remove = stmmac_pltfr_remove,
+ .driver = {
+ .name = "spacemit-dwmac",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = spacemit_dwmac_match,
+ },
+};
+module_platform_driver(spacemit_dwmac_driver);
+
+MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>");
+MODULE_DESCRIPTION("Spacemit DWMAC platform driver");
+MODULE_LICENSE("GPL");
--
2.52.0On Wed, Jan 28, 2026 at 03:29:29PM +0800, Inochi Amaoto wrote: > +#include <linux/clk.h> > +#include <linux/math.h> > +#include <linux/mod_devicetable.h> > +#include <linux/module.h> > +#include <linux/mfd/syscon.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/property.h> > +#include <linux/regmap.h> > + > +#include "stmmac_platform.h" > + > +/* ctrl register bits */ > +#define PHY_INTF_RGMII BIT(3) > +#define PHY_INTF_MII BIT(4) Please add a suitable prefix for these. > + > +#define WAKE_IRQ_EN BIT(9) > +#define PHY_IRQ_EN BIT(12) While you're renaming the PHY_INTF_*, you might wish to also add the same prefix here to identify that they're all part of the same register. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
On Wed, Jan 28, 2026 at 10:43:35AM +0000, Russell King (Oracle) wrote: > On Wed, Jan 28, 2026 at 03:29:29PM +0800, Inochi Amaoto wrote: > > +#include <linux/clk.h> > > +#include <linux/math.h> > > +#include <linux/mod_devicetable.h> > > +#include <linux/module.h> > > +#include <linux/mfd/syscon.h> > > +#include <linux/of.h> > > +#include <linux/platform_device.h> > > +#include <linux/property.h> > > +#include <linux/regmap.h> > > + > > +#include "stmmac_platform.h" > > + > > +/* ctrl register bits */ > > +#define PHY_INTF_RGMII BIT(3) > > +#define PHY_INTF_MII BIT(4) > > Please add a suitable prefix for these. > > > + > > +#define WAKE_IRQ_EN BIT(9) > > +#define PHY_IRQ_EN BIT(12) > > While you're renaming the PHY_INTF_*, you might wish to also add the > same prefix here to identify that they're all part of the same register. > I think this is good for me. I will add the "CTRL" prefix to identify these are all from ctrl register. Regards, Inochi
Hi Inochi,
I have some comments below.
On 1/28/26 15:29, Inochi Amaoto wrote:
> The etherenet controller on Spacemit K3 SoC is Synopsys DesignWare
Typo: etherenet -> ethernet
> MAC (version 5.40a), with the following special point:
Nit: point -> points
> 1. The rate of the tx clock line is auto changed when the mac speed
> rate is changed, and no need for changing the input tx clock.
> 2. This controller require a extra syscon device to configure the
> interface type, enable wake up interrupt and delay configuration
> if needed.
>
> Add Spacemit dwmac driver support on the Spacemit K3 SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 +
> drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 218 ++++++++++++++++++
> 3 files changed, 231 insertions(+)
> create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
>
> [...]
>
> +
> +/* dline register bits */
> +#define RGMII_RX_DLINE_EN BIT(0)
> +#define RGMII_RX_DLINE_STEP GENMASK(5, 4)
> +#define RGMII_RX_DLINE_CODE GENMASK(15, 8)
> +#define RGMII_TX_DLINE_EN BIT(16)
> +#define RGMII_TX_DLINE_STEP GENMASK(21, 20)
> +#define RGMII_TX_DLINE_CODE GENMASK(31, 24)
> +
> +#define MAX_DLINE_DELAY_CODE 0xff
> +#define MAX_WORKED_DELAY 2800
> +
> +/* Note: the delay step value is at 0.1ps */
> +static const unsigned int k3_delay_step_10x[4] = {
> + 367, 493, 559, 685
> +};
> +
> +static int spacemit_dwmac_set_delay(struct regmap *apmu,
> + unsigned int dline_offset,
> + unsigned int tx_code, unsigned int tx_config,
> + unsigned int rx_code, unsigned int rx_config)
> +{
> + unsigned int mask, val;
> +
> + mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN |
> + RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN;
> + val = FIELD_PREP(RGMII_TX_DLINE_STEP, tx_config) |
> + FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN |
> + FIELD_PREP(RGMII_RX_DLINE_STEP, rx_config) |
> + FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN;
> +
> + return regmap_update_bits(apmu, dline_offset, mask, val);
> +}
> +
> +static int spacemit_dwmac_detected_delay_value(unsigned int delay,
> + unsigned int *config)
> +{
> + unsigned int best_delay = 0;
> + unsigned int best_config = 0;
> + int best_code = 0;
> + int i;
> +
> + if (delay == 0)
> + return 0;
> +
> + if (delay > MAX_WORKED_DELAY)
> + return -EINVAL;
> +
> + /*
> + * Note K3 require a specific factor for calculate
> + * the delay, in this scenario it is 0.9. So the
> + * formula is code * step / 10 * 0.9
> + */
> + for (i = 0; i < ARRAY_SIZE(k3_delay_step_10x); i++) {
> + unsigned int step = k3_delay_step_10x[i];
> + int code = DIV_ROUND_CLOSEST(delay * 10 * 10, step * 9);
> + unsigned int tmp = code * step * 9 / 10 / 10;
> +
> + if (abs(tmp - delay) < abs(best_delay - delay)) {
> + best_code = code;
> + best_delay = tmp;
> + best_config = i;
> + }
> + }
> +
> + *config = best_config;
> +
> + return best_code;
Is this really necessary? For K1 I just used the smallest step size.
It seems to me you have, for the smallest step size, about 36.7ps * 0.9
= 33ps per step. Theoretically speaking that lets you fine tune the
delay to within 1% of the 2ns total required RGMII delay (MAC + PCB +
PHY). In practice this number shouldn't be that marginal.
On Wed, Jan 28, 2026 at 05:16:46PM +0800, Vivian Wang wrote:
> Hi Inochi,
>
> I have some comments below.
>
> On 1/28/26 15:29, Inochi Amaoto wrote:
> > The etherenet controller on Spacemit K3 SoC is Synopsys DesignWare
> Typo: etherenet -> ethernet
> > MAC (version 5.40a), with the following special point:
> Nit: point -> points
Thanks
> > 1. The rate of the tx clock line is auto changed when the mac speed
> > rate is changed, and no need for changing the input tx clock.
> > 2. This controller require a extra syscon device to configure the
> > interface type, enable wake up interrupt and delay configuration
> > if needed.
> >
> > Add Spacemit dwmac driver support on the Spacemit K3 SoC.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 +
> > drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
> > .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 218 ++++++++++++++++++
> > 3 files changed, 231 insertions(+)
> > create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
> >
> > [...]
> >
> > +
> > +/* dline register bits */
> > +#define RGMII_RX_DLINE_EN BIT(0)
> > +#define RGMII_RX_DLINE_STEP GENMASK(5, 4)
> > +#define RGMII_RX_DLINE_CODE GENMASK(15, 8)
> > +#define RGMII_TX_DLINE_EN BIT(16)
> > +#define RGMII_TX_DLINE_STEP GENMASK(21, 20)
> > +#define RGMII_TX_DLINE_CODE GENMASK(31, 24)
> > +
> > +#define MAX_DLINE_DELAY_CODE 0xff
> > +#define MAX_WORKED_DELAY 2800
> > +
> > +/* Note: the delay step value is at 0.1ps */
> > +static const unsigned int k3_delay_step_10x[4] = {
> > + 367, 493, 559, 685
> > +};
> > +
> > +static int spacemit_dwmac_set_delay(struct regmap *apmu,
> > + unsigned int dline_offset,
> > + unsigned int tx_code, unsigned int tx_config,
> > + unsigned int rx_code, unsigned int rx_config)
> > +{
> > + unsigned int mask, val;
> > +
> > + mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN |
> > + RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN;
> > + val = FIELD_PREP(RGMII_TX_DLINE_STEP, tx_config) |
> > + FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN |
> > + FIELD_PREP(RGMII_RX_DLINE_STEP, rx_config) |
> > + FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN;
> > +
> > + return regmap_update_bits(apmu, dline_offset, mask, val);
> > +}
> > +
> > +static int spacemit_dwmac_detected_delay_value(unsigned int delay,
> > + unsigned int *config)
> > +{
> > + unsigned int best_delay = 0;
> > + unsigned int best_config = 0;
> > + int best_code = 0;
> > + int i;
> > +
> > + if (delay == 0)
> > + return 0;
> > +
> > + if (delay > MAX_WORKED_DELAY)
> > + return -EINVAL;
> > +
> > + /*
> > + * Note K3 require a specific factor for calculate
> > + * the delay, in this scenario it is 0.9. So the
> > + * formula is code * step / 10 * 0.9
> > + */
> > + for (i = 0; i < ARRAY_SIZE(k3_delay_step_10x); i++) {
> > + unsigned int step = k3_delay_step_10x[i];
> > + int code = DIV_ROUND_CLOSEST(delay * 10 * 10, step * 9);
> > + unsigned int tmp = code * step * 9 / 10 / 10;
> > +
> > + if (abs(tmp - delay) < abs(best_delay - delay)) {
> > + best_code = code;
> > + best_delay = tmp;
> > + best_config = i;
> > + }
> > + }
> > +
> > + *config = best_config;
> > +
> > + return best_code;
>
> Is this really necessary? For K1 I just used the smallest step size.
>
> It seems to me you have, for the smallest step size, about 36.7ps * 0.9
> = 33ps per step. Theoretically speaking that lets you fine tune the
> delay to within 1% of the 2ns total required RGMII delay (MAC + PCB +
> PHY). In practice this number shouldn't be that marginal.
>
I think it is reasonable, I will take you advice and use the
smallest step size.
Regards,
Inochi
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