] arm64: dts: qcom: hamoa: Enable cpufreq cooling devices

[[PATCH]] arm64: dts: qcom: hamoa: Enable cpufreq cooling devices

Posted by Gaurav Kohli 1 week, 3 days ago

Add cooling-cells property to the CPU nodes to support cpufreq
cooling devices.

Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index db65c392e618..799e405a9f87 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -75,6 +75,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&l2_0>;
 			power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 
 			l2_0: l2-cache {
 				compatible = "cache";
@@ -91,6 +92,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&l2_0>;
 			power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@200 {
@@ -101,6 +103,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&l2_0>;
 			power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@300 {
@@ -111,6 +114,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&l2_0>;
 			power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu4: cpu@10000 {
@@ -121,6 +125,7 @@ cpu4: cpu@10000 {
 			next-level-cache = <&l2_1>;
 			power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 
 			l2_1: l2-cache {
 				compatible = "cache";
@@ -137,6 +142,7 @@ cpu5: cpu@10100 {
 			next-level-cache = <&l2_1>;
 			power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu6: cpu@10200 {
@@ -147,6 +153,7 @@ cpu6: cpu@10200 {
 			next-level-cache = <&l2_1>;
 			power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu7: cpu@10300 {
@@ -157,6 +164,7 @@ cpu7: cpu@10300 {
 			next-level-cache = <&l2_1>;
 			power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu8: cpu@20000 {
@@ -167,6 +175,7 @@ cpu8: cpu@20000 {
 			next-level-cache = <&l2_2>;
 			power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 
 			l2_2: l2-cache {
 				compatible = "cache";
@@ -183,6 +192,7 @@ cpu9: cpu@20100 {
 			next-level-cache = <&l2_2>;
 			power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu10: cpu@20200 {
@@ -193,6 +203,7 @@ cpu10: cpu@20200 {
 			next-level-cache = <&l2_2>;
 			power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu11: cpu@20300 {
@@ -203,6 +214,7 @@ cpu11: cpu@20300 {
 			next-level-cache = <&l2_2>;
 			power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
 			power-domain-names = "psci", "perf";
+			#cooling-cells = <2>;
 		};
 
 		cpu-map {
-- 
2.34.1

Re: [[PATCH]] arm64: dts: qcom: hamoa: Enable cpufreq cooling devices

Posted by Manivannan Sadhasivam 4 days, 22 hours ago

On Wed, Jan 28, 2026 at 11:02:08AM +0530, Gaurav Kohli wrote:
> Add cooling-cells property to the CPU nodes to support cpufreq
> cooling devices.
> 
> Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>

FYI: I submitted the similar version back in October:
https://lore.kernel.org/linux-arm-msm/20251015065703.9422-1-mani@kernel.org/

- Mani

> ---
>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index db65c392e618..799e405a9f87 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -75,6 +75,7 @@ cpu0: cpu@0 {
>  			next-level-cache = <&l2_0>;
>  			power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  
>  			l2_0: l2-cache {
>  				compatible = "cache";
> @@ -91,6 +92,7 @@ cpu1: cpu@100 {
>  			next-level-cache = <&l2_0>;
>  			power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu2: cpu@200 {
> @@ -101,6 +103,7 @@ cpu2: cpu@200 {
>  			next-level-cache = <&l2_0>;
>  			power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu3: cpu@300 {
> @@ -111,6 +114,7 @@ cpu3: cpu@300 {
>  			next-level-cache = <&l2_0>;
>  			power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu4: cpu@10000 {
> @@ -121,6 +125,7 @@ cpu4: cpu@10000 {
>  			next-level-cache = <&l2_1>;
>  			power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  
>  			l2_1: l2-cache {
>  				compatible = "cache";
> @@ -137,6 +142,7 @@ cpu5: cpu@10100 {
>  			next-level-cache = <&l2_1>;
>  			power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu6: cpu@10200 {
> @@ -147,6 +153,7 @@ cpu6: cpu@10200 {
>  			next-level-cache = <&l2_1>;
>  			power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu7: cpu@10300 {
> @@ -157,6 +164,7 @@ cpu7: cpu@10300 {
>  			next-level-cache = <&l2_1>;
>  			power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu8: cpu@20000 {
> @@ -167,6 +175,7 @@ cpu8: cpu@20000 {
>  			next-level-cache = <&l2_2>;
>  			power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  
>  			l2_2: l2-cache {
>  				compatible = "cache";
> @@ -183,6 +192,7 @@ cpu9: cpu@20100 {
>  			next-level-cache = <&l2_2>;
>  			power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu10: cpu@20200 {
> @@ -193,6 +203,7 @@ cpu10: cpu@20200 {
>  			next-level-cache = <&l2_2>;
>  			power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu11: cpu@20300 {
> @@ -203,6 +214,7 @@ cpu11: cpu@20300 {
>  			next-level-cache = <&l2_2>;
>  			power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;
>  		};
>  
>  		cpu-map {
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [[PATCH]] arm64: dts: qcom: hamoa: Enable cpufreq cooling devices

Posted by Konrad Dybcio 1 week, 3 days ago

On 1/28/26 6:32 AM, Gaurav Kohli wrote:
> Add cooling-cells property to the CPU nodes to support cpufreq
> cooling devices.
> 
> Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
> ---

The subject has one level of square braces too many, which makes
tooling grumpy


>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index db65c392e618..799e405a9f87 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -75,6 +75,7 @@ cpu0: cpu@0 {
>  			next-level-cache = <&l2_0>;
>  			power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
>  			power-domain-names = "psci", "perf";
> +			#cooling-cells = <2>;

If we're making this change, I think it'd make sense to do so
for all SoCs with some form of cpufreq, since being able to
throttle the CPUs is no less than desired..

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad