arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)
From: Xilin Wu <wuxilin123@gmail.com>
The original values provided by Qualcomm appear to be quite
inaccurate. Specifically, some heavy gaming tasks could be
improperly assigned to the A510 cores by the scheduler, resulting
in a CPU bottleneck. This update to the EAS properties aims to
enhance the user experience across various scenarios.
The power numbers were obtained using a Type-C power meter, which
was directly connected to the battery connector on the AYN Odin 2
motherboard, acting as a fake battery.
It should be noted that the A715 cores seem less efficient than the
A710 cores. Therefore, an average value has been assigned to them,
considering that the A715 and A710 cores share a single cpufreq
domain.
Cortex-A510 cores:
441 kHz, 564 mV, 43 mW, 350 Cx
556 kHz, 580 mV, 59 mW, 346 Cx
672 kHz, 592 mV, 71 mW, 312 Cx
787 kHz, 604 mV, 83 mW, 290 Cx
902 kHz, 608 mV, 96 mW, 288 Cx
1017 kHz, 624 mV, 107 mW, 264 Cx
1113 kHz, 636 mV, 117 mW, 252 Cx
1228 kHz, 652 mV, 130 mW, 240 Cx
1344 kHz, 668 mV, 146 mW, 235 Cx
1459 kHz, 688 mV, 155 mW, 214 Cx
1555 kHz, 704 mV, 166 mW, 205 Cx
1670 kHz, 724 mV, 178 mW, 192 Cx
1785 kHz, 744 mV, 197 mW, 189 Cx
1900 kHz, 764 mV, 221 mW, 190 Cx
2016 kHz, 784 mV, 243 mW, 188 Cx
Your dynamic-power-coefficient for cpu 1: 251
Cortex-A715 cores:
614 kHz, 572 mV, 97 mW, 470 Cx
729 kHz, 592 mV, 123 mW, 473 Cx
844 kHz, 608 mV, 152 mW, 486 Cx
940 kHz, 624 mV, 178 mW, 485 Cx
1056 kHz, 644 mV, 207 mW, 465 Cx
1171 kHz, 656 mV, 243 mW, 480 Cx
1286 kHz, 672 mV, 271 mW, 459 Cx
1401 kHz, 692 mV, 310 mW, 454 Cx
1536 kHz, 716 mV, 368 mW, 462 Cx
1651 kHz, 740 mV, 416 mW, 454 Cx
1785 kHz, 760 mV, 492 mW, 475 Cx
1920 kHz, 784 mV, 544 mW, 457 Cx
2054 kHz, 804 mV, 613 mW, 458 Cx
2188 kHz, 828 mV, 702 mW, 465 Cx
2323 kHz, 852 mV, 782 mW, 461 Cx
2457 kHz, 876 mV, 895 mW, 473 Cx
2592 kHz, 896 mV, 1020 mW, 490 Cx
2707 kHz, 920 mV, 1140 mW, 498 Cx
2803 kHz, 940 mV, 1215 mW, 490 Cx
Your dynamic-power-coefficient for cpu 3: 472
Cortex-A710 cores:
614 kHz, 572 mV, 91 mW, 388 Cx
729 kHz, 592 mV, 116 mW, 424 Cx
844 kHz, 608 mV, 143 mW, 443 Cx
940 kHz, 624 mV, 165 mW, 434 Cx
1056 kHz, 644 mV, 195 mW, 430 Cx
1171 kHz, 656 mV, 218 mW, 414 Cx
1286 kHz, 672 mV, 250 mW, 415 Cx
1401 kHz, 692 mV, 286 mW, 412 Cx
1536 kHz, 716 mV, 331 mW, 407 Cx
1651 kHz, 740 mV, 374 mW, 401 Cx
1785 kHz, 760 mV, 439 mW, 417 Cx
1920 kHz, 784 mV, 495 mW, 411 Cx
2054 kHz, 804 mV, 557 mW, 412 Cx
2188 kHz, 828 mV, 632 mW, 415 Cx
2323 kHz, 852 mV, 721 mW, 422 Cx
2457 kHz, 876 mV, 813 mW, 427 Cx
2592 kHz, 896 mV, 912 mW, 435 Cx
2707 kHz, 920 mV, 1019 mW, 442 Cx
2803 kHz, 940 mV, 1087 mW, 436 Cx
Your dynamic-power-coefficient for cpu 5: 421
Cortex-X3 core:
729 kHz, 568 mV, 252 mW, 1110 Cx
864 kHz, 580 mV, 312 mW, 1097 Cx
998 kHz, 592 mV, 379 mW, 1109 Cx
1132 kHz, 608 mV, 453 mW, 1099 Cx
1248 kHz, 624 mV, 517 mW, 1067 Cx
1363 kHz, 636 mV, 587 mW, 1067 Cx
1478 kHz, 648 mV, 657 mW, 1058 Cx
1593 kHz, 664 mV, 739 mW, 1049 Cx
1708 kHz, 680 mV, 813 mW, 1020 Cx
1843 kHz, 704 mV, 940 mW, 1021 Cx
1977 kHz, 724 mV, 1054 mW, 1007 Cx
2092 kHz, 740 mV, 1201 mW, 1045 Cx
2227 kHz, 768 mV, 1358 mW, 1029 Cx
2342 kHz, 788 mV, 1486 mW, 1016 Cx
2476 kHz, 812 mV, 1711 mW, 1046 Cx
2592 kHz, 836 mV, 1846 mW, 1014 Cx
2726 kHz, 856 mV, 2046 mW, 1020 Cx
2841 kHz, 880 mV, 2266 mW, 1027 Cx
2956 kHz, 908 mV, 2616 mW, 1074 Cx
3187 kHz, 956 mV, 3326 mW, 1147 Cx
Your dynamic-power-coefficient for cpu 7: 1057
7-zip benchmark single-core MIPS:
2128 4416 4632 6686
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..7bbbf3109bc2c6e2e6445207cc86c401be482a73 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -76,8 +76,8 @@ cpu0: cpu@0 {
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -102,8 +102,8 @@ cpu1: cpu@100 {
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
l2_100: l2-cache {
compatible = "cache";
@@ -123,8 +123,8 @@ cpu2: cpu@200 {
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- capacity-dmips-mhz = <1024>;
- dynamic-power-coefficient = <100>;
+ capacity-dmips-mhz = <326>;
+ dynamic-power-coefficient = <251>;
#cooling-cells = <2>;
l2_200: l2-cache {
compatible = "cache";
@@ -144,8 +144,8 @@ cpu3: cpu@300 {
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
@@ -165,8 +165,8 @@ cpu4: cpu@400 {
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
l2_400: l2-cache {
compatible = "cache";
@@ -186,8 +186,8 @@ cpu5: cpu@500 {
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
l2_500: l2-cache {
compatible = "cache";
@@ -207,8 +207,8 @@ cpu6: cpu@600 {
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- capacity-dmips-mhz = <1792>;
- dynamic-power-coefficient = <270>;
+ capacity-dmips-mhz = <693>;
+ dynamic-power-coefficient = <447>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
@@ -228,8 +228,8 @@ cpu7: cpu@700 {
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
- capacity-dmips-mhz = <1894>;
- dynamic-power-coefficient = <588>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <1057>;
#cooling-cells = <2>;
l2_700: l2-cache {
compatible = "cache";
---
base-commit: 3f24e4edcd1b8981c6b448ea2680726dedd87279
change-id: 20260128-sm8550-eas-cdaffda7f779
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@gmail.com>
>
> The original values provided by Qualcomm appear to be quite
> inaccurate. Specifically, some heavy gaming tasks could be
> improperly assigned to the A510 cores by the scheduler, resulting
> in a CPU bottleneck. This update to the EAS properties aims to
> enhance the user experience across various scenarios.
>
> The power numbers were obtained using a Type-C power meter, which
> was directly connected to the battery connector on the AYN Odin 2
> motherboard, acting as a fake battery.
>
> It should be noted that the A715 cores seem less efficient than the
> A710 cores. Therefore, an average value has been assigned to them,
> considering that the A715 and A710 cores share a single cpufreq
> domain.
FWIW the A715s each have 512 kiB of L2, compared to the 256 on the
A710s, which definitely contributes to the power draw. The X core
has 1MiB.
But we have to take that into account, given if the core is online,
so is its cache.
Regarding the CPUFreq domain shared across cores with different power
characteristics, I think we shouldn't be lying to the OS, rather Linux
should be able to deal with it, somehow.
Maybe +CPUFreq/EM maintainers know whether it can do so today
Konrad
>
> Cortex-A510 cores:
> 441 kHz, 564 mV, 43 mW, 350 Cx
> 556 kHz, 580 mV, 59 mW, 346 Cx
> 672 kHz, 592 mV, 71 mW, 312 Cx
> 787 kHz, 604 mV, 83 mW, 290 Cx
> 902 kHz, 608 mV, 96 mW, 288 Cx
> 1017 kHz, 624 mV, 107 mW, 264 Cx
> 1113 kHz, 636 mV, 117 mW, 252 Cx
> 1228 kHz, 652 mV, 130 mW, 240 Cx
> 1344 kHz, 668 mV, 146 mW, 235 Cx
> 1459 kHz, 688 mV, 155 mW, 214 Cx
> 1555 kHz, 704 mV, 166 mW, 205 Cx
> 1670 kHz, 724 mV, 178 mW, 192 Cx
> 1785 kHz, 744 mV, 197 mW, 189 Cx
> 1900 kHz, 764 mV, 221 mW, 190 Cx
> 2016 kHz, 784 mV, 243 mW, 188 Cx
> Your dynamic-power-coefficient for cpu 1: 251
>
> Cortex-A715 cores:
> 614 kHz, 572 mV, 97 mW, 470 Cx
> 729 kHz, 592 mV, 123 mW, 473 Cx
> 844 kHz, 608 mV, 152 mW, 486 Cx
> 940 kHz, 624 mV, 178 mW, 485 Cx
> 1056 kHz, 644 mV, 207 mW, 465 Cx
> 1171 kHz, 656 mV, 243 mW, 480 Cx
> 1286 kHz, 672 mV, 271 mW, 459 Cx
> 1401 kHz, 692 mV, 310 mW, 454 Cx
> 1536 kHz, 716 mV, 368 mW, 462 Cx
> 1651 kHz, 740 mV, 416 mW, 454 Cx
> 1785 kHz, 760 mV, 492 mW, 475 Cx
> 1920 kHz, 784 mV, 544 mW, 457 Cx
> 2054 kHz, 804 mV, 613 mW, 458 Cx
> 2188 kHz, 828 mV, 702 mW, 465 Cx
> 2323 kHz, 852 mV, 782 mW, 461 Cx
> 2457 kHz, 876 mV, 895 mW, 473 Cx
> 2592 kHz, 896 mV, 1020 mW, 490 Cx
> 2707 kHz, 920 mV, 1140 mW, 498 Cx
> 2803 kHz, 940 mV, 1215 mW, 490 Cx
> Your dynamic-power-coefficient for cpu 3: 472
>
> Cortex-A710 cores:
> 614 kHz, 572 mV, 91 mW, 388 Cx
> 729 kHz, 592 mV, 116 mW, 424 Cx
> 844 kHz, 608 mV, 143 mW, 443 Cx
> 940 kHz, 624 mV, 165 mW, 434 Cx
> 1056 kHz, 644 mV, 195 mW, 430 Cx
> 1171 kHz, 656 mV, 218 mW, 414 Cx
> 1286 kHz, 672 mV, 250 mW, 415 Cx
> 1401 kHz, 692 mV, 286 mW, 412 Cx
> 1536 kHz, 716 mV, 331 mW, 407 Cx
> 1651 kHz, 740 mV, 374 mW, 401 Cx
> 1785 kHz, 760 mV, 439 mW, 417 Cx
> 1920 kHz, 784 mV, 495 mW, 411 Cx
> 2054 kHz, 804 mV, 557 mW, 412 Cx
> 2188 kHz, 828 mV, 632 mW, 415 Cx
> 2323 kHz, 852 mV, 721 mW, 422 Cx
> 2457 kHz, 876 mV, 813 mW, 427 Cx
> 2592 kHz, 896 mV, 912 mW, 435 Cx
> 2707 kHz, 920 mV, 1019 mW, 442 Cx
> 2803 kHz, 940 mV, 1087 mW, 436 Cx
> Your dynamic-power-coefficient for cpu 5: 421
>
> Cortex-X3 core:
> 729 kHz, 568 mV, 252 mW, 1110 Cx
> 864 kHz, 580 mV, 312 mW, 1097 Cx
> 998 kHz, 592 mV, 379 mW, 1109 Cx
> 1132 kHz, 608 mV, 453 mW, 1099 Cx
> 1248 kHz, 624 mV, 517 mW, 1067 Cx
> 1363 kHz, 636 mV, 587 mW, 1067 Cx
> 1478 kHz, 648 mV, 657 mW, 1058 Cx
> 1593 kHz, 664 mV, 739 mW, 1049 Cx
> 1708 kHz, 680 mV, 813 mW, 1020 Cx
> 1843 kHz, 704 mV, 940 mW, 1021 Cx
> 1977 kHz, 724 mV, 1054 mW, 1007 Cx
> 2092 kHz, 740 mV, 1201 mW, 1045 Cx
> 2227 kHz, 768 mV, 1358 mW, 1029 Cx
> 2342 kHz, 788 mV, 1486 mW, 1016 Cx
> 2476 kHz, 812 mV, 1711 mW, 1046 Cx
> 2592 kHz, 836 mV, 1846 mW, 1014 Cx
> 2726 kHz, 856 mV, 2046 mW, 1020 Cx
> 2841 kHz, 880 mV, 2266 mW, 1027 Cx
> 2956 kHz, 908 mV, 2616 mW, 1074 Cx
> 3187 kHz, 956 mV, 3326 mW, 1147 Cx
> Your dynamic-power-coefficient for cpu 7: 1057
>
> 7-zip benchmark single-core MIPS:
> 2128 4416 4632 6686
>
> Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..7bbbf3109bc2c6e2e6445207cc86c401be482a73 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -76,8 +76,8 @@ cpu0: cpu@0 {
> power-domains = <&cpu_pd0>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> - capacity-dmips-mhz = <1024>;
> - dynamic-power-coefficient = <100>;
> + capacity-dmips-mhz = <326>;
> + dynamic-power-coefficient = <251>;
> #cooling-cells = <2>;
> l2_0: l2-cache {
> compatible = "cache";
> @@ -102,8 +102,8 @@ cpu1: cpu@100 {
> power-domains = <&cpu_pd1>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> - capacity-dmips-mhz = <1024>;
> - dynamic-power-coefficient = <100>;
> + capacity-dmips-mhz = <326>;
> + dynamic-power-coefficient = <251>;
> #cooling-cells = <2>;
> l2_100: l2-cache {
> compatible = "cache";
> @@ -123,8 +123,8 @@ cpu2: cpu@200 {
> power-domains = <&cpu_pd2>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> - capacity-dmips-mhz = <1024>;
> - dynamic-power-coefficient = <100>;
> + capacity-dmips-mhz = <326>;
> + dynamic-power-coefficient = <251>;
> #cooling-cells = <2>;
> l2_200: l2-cache {
> compatible = "cache";
> @@ -144,8 +144,8 @@ cpu3: cpu@300 {
> power-domains = <&cpu_pd3>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_300: l2-cache {
> compatible = "cache";
> @@ -165,8 +165,8 @@ cpu4: cpu@400 {
> power-domains = <&cpu_pd4>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_400: l2-cache {
> compatible = "cache";
> @@ -186,8 +186,8 @@ cpu5: cpu@500 {
> power-domains = <&cpu_pd5>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_500: l2-cache {
> compatible = "cache";
> @@ -207,8 +207,8 @@ cpu6: cpu@600 {
> power-domains = <&cpu_pd6>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_600: l2-cache {
> compatible = "cache";
> @@ -228,8 +228,8 @@ cpu7: cpu@700 {
> power-domains = <&cpu_pd7>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 2>;
> - capacity-dmips-mhz = <1894>;
> - dynamic-power-coefficient = <588>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <1057>;
> #cooling-cells = <2>;
> l2_700: l2-cache {
> compatible = "cache";
>
> ---
> base-commit: 3f24e4edcd1b8981c6b448ea2680726dedd87279
> change-id: 20260128-sm8550-eas-cdaffda7f779
>
> Best regards,
On 29-01-26, 12:00, Konrad Dybcio wrote: > On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: > > It should be noted that the A715 cores seem less efficient than the > > A710 cores. Therefore, an average value has been assigned to them, > > considering that the A715 and A710 cores share a single cpufreq > > domain. > > Regarding the CPUFreq domain shared across cores with different power > characteristics, I think we shouldn't be lying to the OS, rather Linux > should be able to deal with it, somehow. cpufreq-domain == cpufreq-policy here I guess. All CPUs that change their DVFS state together should be part of one policy. Not sure if there is something else you were pointing at. -- viresh
On 1/29/26 12:05 PM, Viresh Kumar wrote: > On 29-01-26, 12:00, Konrad Dybcio wrote: >> On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: >>> It should be noted that the A715 cores seem less efficient than the >>> A710 cores. Therefore, an average value has been assigned to them, >>> considering that the A715 and A710 cores share a single cpufreq >>> domain. >> >> Regarding the CPUFreq domain shared across cores with different power >> characteristics, I think we shouldn't be lying to the OS, rather Linux >> should be able to deal with it, somehow. > > cpufreq-domain == cpufreq-policy here I guess. All CPUs that change > their DVFS state together should be part of one policy. Not sure if > there is something else you were pointing at. Yes, they change their state together. The question is whether it's okay for these CPUs to have different dynamic-power-coefficient values, and whether the EM code won't be thrown off by that. Again, they differ because within that shared policy, there's 2 separate kinds of cores (2x Cortex-A715 + 2x Cortex-A710). Konrad
On 1/29/26 11:23, Konrad Dybcio wrote: > On 1/29/26 12:05 PM, Viresh Kumar wrote: >> On 29-01-26, 12:00, Konrad Dybcio wrote: >>> On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: >>>> It should be noted that the A715 cores seem less efficient than the >>>> A710 cores. Therefore, an average value has been assigned to them, >>>> considering that the A715 and A710 cores share a single cpufreq >>>> domain. >>> >>> Regarding the CPUFreq domain shared across cores with different power >>> characteristics, I think we shouldn't be lying to the OS, rather Linux >>> should be able to deal with it, somehow. >> >> cpufreq-domain == cpufreq-policy here I guess. All CPUs that change >> their DVFS state together should be part of one policy. Not sure if >> there is something else you were pointing at. > > Yes, they change their state together. > > The question is whether it's okay for these CPUs to have different > dynamic-power-coefficient values, and whether the EM code won't be > thrown off by that. The Energy Model won't support that, since it's a single instance per-cpufreq-policy and we have to pick 'some' values (in this case). > > Again, they differ because within that shared policy, there's 2 > separate kinds of cores (2x Cortex-A715 + 2x Cortex-A710). > For this SoC I assume the physical HW (power rail and frequency domain) is linked to those 4 CPUs. That's quite novel configuration... Maybe I could give you some hint at least for the EAS part (the EM for EAS), because for something in other areas (e.g. thermal) might be really tough. What are the other CPUs in that SoC and their DVFS configs? Regards, Lukasz
On 1/29/26 12:38 PM, Lukasz Luba wrote: > > > On 1/29/26 11:23, Konrad Dybcio wrote: >> On 1/29/26 12:05 PM, Viresh Kumar wrote: >>> On 29-01-26, 12:00, Konrad Dybcio wrote: >>>> On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: >>>>> It should be noted that the A715 cores seem less efficient than the >>>>> A710 cores. Therefore, an average value has been assigned to them, >>>>> considering that the A715 and A710 cores share a single cpufreq >>>>> domain. >>>> >>>> Regarding the CPUFreq domain shared across cores with different power >>>> characteristics, I think we shouldn't be lying to the OS, rather Linux >>>> should be able to deal with it, somehow. >>> >>> cpufreq-domain == cpufreq-policy here I guess. All CPUs that change >>> their DVFS state together should be part of one policy. Not sure if >>> there is something else you were pointing at. >> >> Yes, they change their state together. >> >> The question is whether it's okay for these CPUs to have different >> dynamic-power-coefficient values, and whether the EM code won't be >> thrown off by that. > > The Energy Model won't support that, since it's a single > instance per-cpufreq-policy and we have to pick 'some' values (in this > case). Do you think taking an average, like suggested by the original author, makes sense here? >> Again, they differ because within that shared policy, there's 2 >> separate kinds of cores (2x Cortex-A715 + 2x Cortex-A710). >> > > For this SoC I assume the physical HW (power rail and frequency domain) > is linked to those 4 CPUs. That's quite novel configuration... > > Maybe I could give you some hint at least for the EAS part (the EM > for EAS), because for something in other areas (e.g. thermal) might > be really tough. In this case, these cores have **fairly** similar power/perf characteristics, as evidenced by the measurements in the root of this thread, see: https://lore.kernel.org/linux-arm-msm/20260128-sm8550-eas-v1-1-fb80615bed5c@gmail.com/ > What are the other CPUs in that SoC and their DVFS configs? Domain 0: 3x A510 Domain 1: 2x A715 + 2x A710 Domain 2: 1x X3 Konrad
On 1/29/26 11:56, Konrad Dybcio wrote: > On 1/29/26 12:38 PM, Lukasz Luba wrote: >> >> >> On 1/29/26 11:23, Konrad Dybcio wrote: >>> On 1/29/26 12:05 PM, Viresh Kumar wrote: >>>> On 29-01-26, 12:00, Konrad Dybcio wrote: >>>>> On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: >>>>>> It should be noted that the A715 cores seem less efficient than the >>>>>> A710 cores. Therefore, an average value has been assigned to them, >>>>>> considering that the A715 and A710 cores share a single cpufreq >>>>>> domain. >>>>> >>>>> Regarding the CPUFreq domain shared across cores with different power >>>>> characteristics, I think we shouldn't be lying to the OS, rather Linux >>>>> should be able to deal with it, somehow. >>>> >>>> cpufreq-domain == cpufreq-policy here I guess. All CPUs that change >>>> their DVFS state together should be part of one policy. Not sure if >>>> there is something else you were pointing at. >>> >>> Yes, they change their state together. >>> >>> The question is whether it's okay for these CPUs to have different >>> dynamic-power-coefficient values, and whether the EM code won't be >>> thrown off by that. >> >> The Energy Model won't support that, since it's a single >> instance per-cpufreq-policy and we have to pick 'some' values (in this >> case). > > Do you think taking an average, like suggested by the original author, > makes sense here? > >>> Again, they differ because within that shared policy, there's 2 >>> separate kinds of cores (2x Cortex-A715 + 2x Cortex-A710). >>> >> >> For this SoC I assume the physical HW (power rail and frequency domain) >> is linked to those 4 CPUs. That's quite novel configuration... >> >> Maybe I could give you some hint at least for the EAS part (the EM >> for EAS), because for something in other areas (e.g. thermal) might >> be really tough. > > In this case, these cores have **fairly** similar power/perf > characteristics, as evidenced by the measurements in the root of > this thread, see: > > https://lore.kernel.org/linux-arm-msm/20260128-sm8550-eas-v1-1-fb80615bed5c@gmail.com/ > >> What are the other CPUs in that SoC and their DVFS configs? > > Domain 0: 3x A510 > Domain 1: 2x A715 + 2x A710 > Domain 2: 1x X3 > I have analyzed that data both: power and performance (the 7-zip benchmark). It looks good and might fly upstream. Although, I wonder if that benchmark truly reflects the workload for that gaming handheld... For 'normal' usage (mix of stuff running on a device, not mainly games) these derived numbers are promising. The plot that I got for the Energy Model shows fairly similar efficiency for a710 and a715 - which is expected. There is also a nice size (60%) of an overlapping region to operate on for the EAS. That would be typical model for day-of-usage with mixed scenario. The platform engineers can later modify the EM data in run-time to better reflect their workload's behavior on the SoC. Since this is mainline change for sm8550 and looks - LGTM. Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Regards, Lukasz
On 2/2/26 10:28 AM, Lukasz Luba wrote: > > > On 1/29/26 11:56, Konrad Dybcio wrote: >> On 1/29/26 12:38 PM, Lukasz Luba wrote: >>> >>> >>> On 1/29/26 11:23, Konrad Dybcio wrote: >>>> On 1/29/26 12:05 PM, Viresh Kumar wrote: >>>>> On 29-01-26, 12:00, Konrad Dybcio wrote: >>>>>> On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: >>>>>>> It should be noted that the A715 cores seem less efficient than the >>>>>>> A710 cores. Therefore, an average value has been assigned to them, >>>>>>> considering that the A715 and A710 cores share a single cpufreq >>>>>>> domain. >>>>>> >>>>>> Regarding the CPUFreq domain shared across cores with different power >>>>>> characteristics, I think we shouldn't be lying to the OS, rather Linux >>>>>> should be able to deal with it, somehow. >>>>> >>>>> cpufreq-domain == cpufreq-policy here I guess. All CPUs that change >>>>> their DVFS state together should be part of one policy. Not sure if >>>>> there is something else you were pointing at. >>>> >>>> Yes, they change their state together. >>>> >>>> The question is whether it's okay for these CPUs to have different >>>> dynamic-power-coefficient values, and whether the EM code won't be >>>> thrown off by that. >>> >>> The Energy Model won't support that, since it's a single >>> instance per-cpufreq-policy and we have to pick 'some' values (in this >>> case). >> >> Do you think taking an average, like suggested by the original author, >> makes sense here? >> >>>> Again, they differ because within that shared policy, there's 2 >>>> separate kinds of cores (2x Cortex-A715 + 2x Cortex-A710). >>>> >>> >>> For this SoC I assume the physical HW (power rail and frequency domain) >>> is linked to those 4 CPUs. That's quite novel configuration... >>> >>> Maybe I could give you some hint at least for the EAS part (the EM >>> for EAS), because for something in other areas (e.g. thermal) might >>> be really tough. >> >> In this case, these cores have **fairly** similar power/perf >> characteristics, as evidenced by the measurements in the root of >> this thread, see: >> >> https://lore.kernel.org/linux-arm-msm/20260128-sm8550-eas-v1-1-fb80615bed5c@gmail.com/ >> >>> What are the other CPUs in that SoC and their DVFS configs? >> >> Domain 0: 3x A510 >> Domain 1: 2x A715 + 2x A710 >> Domain 2: 1x X3 >> > > I have analyzed that data both: power and performance > (the 7-zip benchmark). It looks good and might fly upstream. > Although, I wonder if that benchmark truly reflects the > workload for that gaming handheld... FWIW this is the common SoC DT, the author of the patch only happens to have that SoC inside a gaming handheld > For 'normal' usage (mix of stuff running on a device, not > mainly games) these derived numbers are promising. > The plot that I got for the Energy Model shows fairly > similar efficiency for a710 and a715 - which is expected. > There is also a nice size (60%) of an overlapping region to operate > on for the EAS. That would be typical model for day-of-usage > with mixed scenario. > The platform engineers can later modify the EM data in run-time > to better reflect their workload's behavior on the SoC. > > Since this is mainline change for sm8550 and looks - LGTM. > > Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Thanks for your insight! Konrad
On 1/28/26 20:11, Aaron Kling via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@gmail.com>
>
> The original values provided by Qualcomm appear to be quite
> inaccurate. Specifically, some heavy gaming tasks could be
> improperly assigned to the A510 cores by the scheduler, resulting
> in a CPU bottleneck. This update to the EAS properties aims to
> enhance the user experience across various scenarios.
>
> The power numbers were obtained using a Type-C power meter, which
> was directly connected to the battery connector on the AYN Odin 2
> motherboard, acting as a fake battery.
>
> It should be noted that the A715 cores seem less efficient than the
> A710 cores. Therefore, an average value has been assigned to them,
> considering that the A715 and A710 cores share a single cpufreq
> domain.
>
> Cortex-A510 cores:
> 441 kHz, 564 mV, 43 mW, 350 Cx
> 556 kHz, 580 mV, 59 mW, 346 Cx
> 672 kHz, 592 mV, 71 mW, 312 Cx
> 787 kHz, 604 mV, 83 mW, 290 Cx
> 902 kHz, 608 mV, 96 mW, 288 Cx
> 1017 kHz, 624 mV, 107 mW, 264 Cx
> 1113 kHz, 636 mV, 117 mW, 252 Cx
> 1228 kHz, 652 mV, 130 mW, 240 Cx
> 1344 kHz, 668 mV, 146 mW, 235 Cx
> 1459 kHz, 688 mV, 155 mW, 214 Cx
> 1555 kHz, 704 mV, 166 mW, 205 Cx
> 1670 kHz, 724 mV, 178 mW, 192 Cx
> 1785 kHz, 744 mV, 197 mW, 189 Cx
> 1900 kHz, 764 mV, 221 mW, 190 Cx
> 2016 kHz, 784 mV, 243 mW, 188 Cx
> Your dynamic-power-coefficient for cpu 1: 251
>
> Cortex-A715 cores:
> 614 kHz, 572 mV, 97 mW, 470 Cx
> 729 kHz, 592 mV, 123 mW, 473 Cx
> 844 kHz, 608 mV, 152 mW, 486 Cx
> 940 kHz, 624 mV, 178 mW, 485 Cx
> 1056 kHz, 644 mV, 207 mW, 465 Cx
> 1171 kHz, 656 mV, 243 mW, 480 Cx
> 1286 kHz, 672 mV, 271 mW, 459 Cx
> 1401 kHz, 692 mV, 310 mW, 454 Cx
> 1536 kHz, 716 mV, 368 mW, 462 Cx
> 1651 kHz, 740 mV, 416 mW, 454 Cx
> 1785 kHz, 760 mV, 492 mW, 475 Cx
> 1920 kHz, 784 mV, 544 mW, 457 Cx
> 2054 kHz, 804 mV, 613 mW, 458 Cx
> 2188 kHz, 828 mV, 702 mW, 465 Cx
> 2323 kHz, 852 mV, 782 mW, 461 Cx
> 2457 kHz, 876 mV, 895 mW, 473 Cx
> 2592 kHz, 896 mV, 1020 mW, 490 Cx
> 2707 kHz, 920 mV, 1140 mW, 498 Cx
> 2803 kHz, 940 mV, 1215 mW, 490 Cx
> Your dynamic-power-coefficient for cpu 3: 472
>
> Cortex-A710 cores:
> 614 kHz, 572 mV, 91 mW, 388 Cx
> 729 kHz, 592 mV, 116 mW, 424 Cx
> 844 kHz, 608 mV, 143 mW, 443 Cx
> 940 kHz, 624 mV, 165 mW, 434 Cx
> 1056 kHz, 644 mV, 195 mW, 430 Cx
> 1171 kHz, 656 mV, 218 mW, 414 Cx
> 1286 kHz, 672 mV, 250 mW, 415 Cx
> 1401 kHz, 692 mV, 286 mW, 412 Cx
> 1536 kHz, 716 mV, 331 mW, 407 Cx
> 1651 kHz, 740 mV, 374 mW, 401 Cx
> 1785 kHz, 760 mV, 439 mW, 417 Cx
> 1920 kHz, 784 mV, 495 mW, 411 Cx
> 2054 kHz, 804 mV, 557 mW, 412 Cx
> 2188 kHz, 828 mV, 632 mW, 415 Cx
> 2323 kHz, 852 mV, 721 mW, 422 Cx
> 2457 kHz, 876 mV, 813 mW, 427 Cx
> 2592 kHz, 896 mV, 912 mW, 435 Cx
> 2707 kHz, 920 mV, 1019 mW, 442 Cx
> 2803 kHz, 940 mV, 1087 mW, 436 Cx
> Your dynamic-power-coefficient for cpu 5: 421
>
> Cortex-X3 core:
> 729 kHz, 568 mV, 252 mW, 1110 Cx
> 864 kHz, 580 mV, 312 mW, 1097 Cx
> 998 kHz, 592 mV, 379 mW, 1109 Cx
> 1132 kHz, 608 mV, 453 mW, 1099 Cx
> 1248 kHz, 624 mV, 517 mW, 1067 Cx
> 1363 kHz, 636 mV, 587 mW, 1067 Cx
> 1478 kHz, 648 mV, 657 mW, 1058 Cx
> 1593 kHz, 664 mV, 739 mW, 1049 Cx
> 1708 kHz, 680 mV, 813 mW, 1020 Cx
> 1843 kHz, 704 mV, 940 mW, 1021 Cx
> 1977 kHz, 724 mV, 1054 mW, 1007 Cx
> 2092 kHz, 740 mV, 1201 mW, 1045 Cx
> 2227 kHz, 768 mV, 1358 mW, 1029 Cx
> 2342 kHz, 788 mV, 1486 mW, 1016 Cx
> 2476 kHz, 812 mV, 1711 mW, 1046 Cx
> 2592 kHz, 836 mV, 1846 mW, 1014 Cx
> 2726 kHz, 856 mV, 2046 mW, 1020 Cx
> 2841 kHz, 880 mV, 2266 mW, 1027 Cx
> 2956 kHz, 908 mV, 2616 mW, 1074 Cx
> 3187 kHz, 956 mV, 3326 mW, 1147 Cx
> Your dynamic-power-coefficient for cpu 7: 1057
>
> 7-zip benchmark single-core MIPS:
> 2128 4416 4632 6686
>
> Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++----------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..7bbbf3109bc2c6e2e6445207cc86c401be482a73 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -76,8 +76,8 @@ cpu0: cpu@0 {
> power-domains = <&cpu_pd0>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> - capacity-dmips-mhz = <1024>;
> - dynamic-power-coefficient = <100>;
> + capacity-dmips-mhz = <326>;
> + dynamic-power-coefficient = <251>;
> #cooling-cells = <2>;
> l2_0: l2-cache {
> compatible = "cache";
> @@ -102,8 +102,8 @@ cpu1: cpu@100 {
> power-domains = <&cpu_pd1>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> - capacity-dmips-mhz = <1024>;
> - dynamic-power-coefficient = <100>;
> + capacity-dmips-mhz = <326>;
> + dynamic-power-coefficient = <251>;
> #cooling-cells = <2>;
> l2_100: l2-cache {
> compatible = "cache";
> @@ -123,8 +123,8 @@ cpu2: cpu@200 {
> power-domains = <&cpu_pd2>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 0>;
> - capacity-dmips-mhz = <1024>;
> - dynamic-power-coefficient = <100>;
> + capacity-dmips-mhz = <326>;
> + dynamic-power-coefficient = <251>;
> #cooling-cells = <2>;
> l2_200: l2-cache {
> compatible = "cache";
> @@ -144,8 +144,8 @@ cpu3: cpu@300 {
> power-domains = <&cpu_pd3>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_300: l2-cache {
> compatible = "cache";
> @@ -165,8 +165,8 @@ cpu4: cpu@400 {
> power-domains = <&cpu_pd4>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_400: l2-cache {
> compatible = "cache";
> @@ -186,8 +186,8 @@ cpu5: cpu@500 {
> power-domains = <&cpu_pd5>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_500: l2-cache {
> compatible = "cache";
> @@ -207,8 +207,8 @@ cpu6: cpu@600 {
> power-domains = <&cpu_pd6>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 1>;
> - capacity-dmips-mhz = <1792>;
> - dynamic-power-coefficient = <270>;
> + capacity-dmips-mhz = <693>;
> + dynamic-power-coefficient = <447>;
> #cooling-cells = <2>;
> l2_600: l2-cache {
> compatible = "cache";
> @@ -228,8 +228,8 @@ cpu7: cpu@700 {
> power-domains = <&cpu_pd7>;
> power-domain-names = "psci";
> qcom,freq-domain = <&cpufreq_hw 2>;
> - capacity-dmips-mhz = <1894>;
> - dynamic-power-coefficient = <588>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <1057>;
> #cooling-cells = <2>;
> l2_700: l2-cache {
> compatible = "cache";
>
> ---
> base-commit: 3f24e4edcd1b8981c6b448ea2680726dedd87279
> change-id: 20260128-sm8550-eas-cdaffda7f779
>
> Best regards,
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
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