It appears the i.MX8MP does not like when arm_a53_div, or rather the
parent it depends on, sys_pll2_500m, is briefly turned off during
__clk_core_init.

In the past, this clock driver could get away with not declaring the
clock as critical, as nothing ever fiddled with its parent that early
on. However, after Commit 669917676e93 ("clk: Respect
CLK_OPS_PARENT_ENABLE during recalc"), this changed.

In order to guarantee that it keeps its parent enabled during
__clk_core_init if it sets the flag CLK_OPS_PARENT_ENABLE, the clock
must be marked as critical.

Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Closes: https://lore.kernel.org/r/6239343.lOV4Wx5bFT@steina-w/
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
 drivers/clk/imx/clk-imx8mp.c | 4 +++-
 drivers/clk/imx/clk.h        | 4 ++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index fe6dac70f1a1..ee10f845faff 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -655,7 +655,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
 	hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
 
-	hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
+	hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core_critical("arm_a53_div",
+								       imx8mp_a53_sels,
+								       ccm_base + 0x8000);
 	hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
 	hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
 	hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index aa5202f284f3..97cac1d623ca 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -454,6 +454,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
 	_imx8m_clk_hw_composite(name, parent_names, reg, \
 			IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
 
+#define imx8m_clk_hw_composite_core_critical(name, parent_names, reg)	\
+	_imx8m_clk_hw_composite(name, parent_names, reg, \
+			IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
+
 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
 	_imx8m_clk_hw_composite(name, parent_names, reg, \
 			IMX_COMPOSITE_FW_MANAGED, \

-- 
2.52.0

Hi Nicolas,

I've tested this series on i.MX8MP and unfortunately it doesn't fix the issue.
This is the serial console output: https://pastebin.com/dvJQ0HBy

We can talk privately and can help you test if you have debug patches.

Reverting:

669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")

Makes everything work again.

thanks,
Daniel.

On Wed, Jan 28, 2026 at 8:40 PM Nicolas Frattaroli
<nicolas.frattaroli@collabora.com> wrote:
>
> It appears the i.MX8MP does not like when arm_a53_div, or rather the
> parent it depends on, sys_pll2_500m, is briefly turned off during
> __clk_core_init.
>
> In the past, this clock driver could get away with not declaring the
> clock as critical, as nothing ever fiddled with its parent that early
> on. However, after Commit 669917676e93 ("clk: Respect
> CLK_OPS_PARENT_ENABLE during recalc"), this changed.
>
> In order to guarantee that it keeps its parent enabled during
> __clk_core_init if it sets the flag CLK_OPS_PARENT_ENABLE, the clock
> must be marked as critical.
>
> Fixes: 669917676e93 ("clk: Respect CLK_OPS_PARENT_ENABLE during recalc")
> Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Closes: https://lore.kernel.org/r/6239343.lOV4Wx5bFT@steina-w/
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
>  drivers/clk/imx/clk-imx8mp.c | 4 +++-
>  drivers/clk/imx/clk.h        | 4 ++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index fe6dac70f1a1..ee10f845faff 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -655,7 +655,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>         hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
>         hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
>
> -       hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
> +       hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core_critical("arm_a53_div",
> +                                                                      imx8mp_a53_sels,
> +                                                                      ccm_base + 0x8000);
>         hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
>         hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
>         hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index aa5202f284f3..97cac1d623ca 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -454,6 +454,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
>         _imx8m_clk_hw_composite(name, parent_names, reg, \
>                         IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
>
> +#define imx8m_clk_hw_composite_core_critical(name, parent_names, reg)  \
> +       _imx8m_clk_hw_composite(name, parent_names, reg, \
> +                       IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> +
>  #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
>         _imx8m_clk_hw_composite(name, parent_names, reg, \
>                         IMX_COMPOSITE_FW_MANAGED, \
>
> --
> 2.52.0
>
>