PCIe r6.0, section 7.9.15 requires PTM capability in exactly one
function to control all PTM-capable functions. This makes PTM registers
controller-level rather than per-function.
Add a comment explaining why PTM capability registers are accessed
using the standard DBI accessors instead of func_no indexed
per-function accessors.
Suggested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Aksh Garg <a-garg7@ti.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
---
Changes from v2 to v3:
- Fixed the suggested nits
v2: https://lore.kernel.org/all/20260122082538.309122-4-a-garg7@ti.com/
drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 095362143363..2488690f509b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -995,6 +995,16 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
if (ep->ops->init)
ep->ops->init(ep);
+ /*
+ * PCIe r6.0, section 7.9.15 states that for endpoints that support PTM,
+ * this capability structure is required in exactly one function, which
+ * controls the PTM behavior of all PTM capable functions. This indicates
+ * the PTM capability structure represents controller-level registers
+ * rather than per-function registers.
+ *
+ * Therefore, PTM capability registers are configured using the standard DBI
+ * accessors, instead of func_no indexed per-function accessors.
+ */
ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
/*
--
2.34.1