From: Yu-Chun Lin <eleanor.lin@realtek.com>
Add Device Tree hierarchy for Realtek Kent SoC family:
- kent.dtsi: base SoC layer
- rtd<variant>.dtsi: SoC variant layer
- rtd<variant>-<board>.dtsi: board layer
- rtd<variant>-<board>-<config>.dts: board configuration layer
Include RTD1501s Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and
RTD1920s Smallville EVB (4GB).
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
arch/arm64/boot/dts/realtek/Makefile | 7 +-
arch/arm64/boot/dts/realtek/kent.dtsi | 166 ++++++++++++++++++
arch/arm64/boot/dts/realtek/rtd1501.dtsi | 12 ++
.../boot/dts/realtek/rtd1501s-phantom-8gb.dts | 25 +++
.../boot/dts/realtek/rtd1501s-phantom.dtsi | 118 +++++++++++++
arch/arm64/boot/dts/realtek/rtd1861.dtsi | 12 ++
.../boot/dts/realtek/rtd1861b-krypton-8gb.dts | 25 +++
.../boot/dts/realtek/rtd1861b-krypton.dtsi | 72 ++++++++
arch/arm64/boot/dts/realtek/rtd1920.dtsi | 12 ++
.../dts/realtek/rtd1920s-smallville-4gb.dts | 23 +++
.../boot/dts/realtek/rtd1920s-smallville.dtsi | 128 ++++++++++++++
11 files changed, 596 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/realtek/kent.dtsi
create mode 100644 arch/arm64/boot/dts/realtek/rtd1501.dtsi
create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts
create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi
create mode 100644 arch/arm64/boot/dts/realtek/rtd1861.dtsi
create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts
create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi
create mode 100644 arch/arm64/boot/dts/realtek/rtd1920.dtsi
create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts
create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi
diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile
index ef8d8fcbaa05..60a37d5a948c 100644
--- a/arch/arm64/boot/dts/realtek/Makefile
+++ b/arch/arm64/boot/dts/realtek/Makefile
@@ -1,15 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb
-
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
-
dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
-
dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
-
+dtb-$(CONFIG_ARCH_REALTEK) += rtd1501s-phantom-8gb.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb
+dtb-$(CONFIG_ARCH_REALTEK) += rtd1861b-krypton-8gb.dtb
+dtb-$(CONFIG_ARCH_REALTEK) += rtd1920s-smallville-4gb.dtb
diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
new file mode 100644
index 000000000000..e659bb252759
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/kent.dtsi
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek Kent SoC family
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2_1>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_3>;
+ dynamic-power-coefficient = <454>;
+ #cooling-cells = <2>;
+
+ l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ };
+ };
+
+ l3: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x200000>;
+ cache-unified;
+ };
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
+ <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
+ <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
+ <0xff000000 0x0 0xff000000 0x200000>; /* GIC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ rbus: bus@98000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x98000000 0xef0000>,
+ <0xa0000000 0xa0000000 0x10000000>; /* PCIE */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@7800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x7800 0x100>;
+ clock-frequency = <432000000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@ff100000 {
+ compatible = "arm,gic-v3";
+ reg = <0xff100000 0x10000>,
+ <0xff140000 0x80000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #interrupt-cells = <3>;
+ #size-cells = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts/realtek/rtd1501.dtsi
new file mode 100644
index 000000000000..65f7ede3df73
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1501 SoC
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include "kent.dtsi"
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts
new file mode 100644
index 000000000000..09e544acfd34
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1501S Phantom EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1501s-phantom.dtsi"
+
+/ {
+ compatible = "realtek,phantom", "realtek,rtd1501s";
+ model = "Realtek Phantom EVB Chromium (8GB)";
+
+ memory@40000 {
+ device_type = "memory";
+ reg = <0x0 0x50000 0x0 0x7ffb0000>,
+ <0x0 0x8a100000 0x0 0xdef0000>,
+ <0x0 0x98700000 0x0 0x7900000>,
+ <0x0 0xa0600000 0x0 0x5ea00000>,
+ <0x1 0x0 0x0 0xa0000000>,
+ <0x1 0xa0600000 0x0 0x5fa00000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi
new file mode 100644
index 000000000000..bcfb96799671
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1501S Phantom EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/thermal/thermal.h>
+#include "rtd1501.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:460800n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x0 0x0 0x20000000>;
+ size = <0x0 0x2000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ cpu_opps: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp800: opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <830000 830000 1100000>;
+ };
+
+ opp900: opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000 850000 1100000>;
+ };
+
+ opp1000: opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <870000 870000 1100000>;
+ };
+
+ opp1100: opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <890000 890000 1100000>;
+ };
+
+ opp1200: opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <910000 910000 1100000>;
+ };
+
+ opp1300: opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <930000 930000 1100000>;
+ };
+
+ opp1400: opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000 950000 1100000>;
+ };
+
+ opp1500: opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <970000 970000 1100000>;
+ };
+
+ opp1600: opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <990000 990000 1100000>;
+ opp-suspend;
+ };
+
+ opp1700: opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1010000 1010000 1100000>;
+ };
+
+ opp1800: opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1030000 1030000 1100000>;
+ };
+
+ opp1900: opp-1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1050000 1050000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1861.dtsi b/arch/arm64/boot/dts/realtek/rtd1861.dtsi
new file mode 100644
index 000000000000..44c3de8f1f48
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1861.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1861 SoC
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include "kent.dtsi"
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts
new file mode 100644
index 000000000000..9c23d901c49c
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1861B Krypton EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1861b-krypton.dtsi"
+
+/ {
+ compatible = "realtek,krypton", "realtek,rtd1861b";
+ model = "Realtek Krypton EVB (8GB)";
+
+ memory@40000 {
+ device_type = "memory";
+ reg = <0x0 0x50000 0x0 0x7ffb0000>,
+ <0x0 0x8a100000 0x0 0xdef0000>,
+ <0x0 0x98700000 0x0 0x7900000>,
+ <0x0 0xa0600000 0x0 0x5ea00000>,
+ <0x1 0x0 0x0 0xa0000000>,
+ <0x1 0xa0600000 0x0 0x5fa00000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi
new file mode 100644
index 000000000000..b500f4d2c502
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1861B Krypton EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1861.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:460800n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x0 0x0 0x20000000>;
+ size = <0x0 0x2000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ cpu_opps: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp1200: opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <900000>;
+ };
+
+ opp1600: opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1000000>;
+ opp-suspend;
+ };
+
+ opp1800: opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1920.dtsi b/arch/arm64/boot/dts/realtek/rtd1920.dtsi
new file mode 100644
index 000000000000..becf546216e9
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1920.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1920 SoC
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+#include "kent.dtsi"
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts
new file mode 100644
index 000000000000..9fd6976e0d9b
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1920S Smallville EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd1920s-smallville.dtsi"
+
+/ {
+ compatible = "realtek,smallville", "realtek,rtd1920s";
+ model = "Realtek Smallville EVB (4GB)";
+
+ memory@40000 {
+ device_type = "memory";
+ reg = <0x0 0x50000 0x0 0x7ffb0000>,
+ <0x0 0x8a100000 0x0 0xdef0000>,
+ <0x0 0x98700000 0x0 0x7900000>,
+ <0x0 0xa1000000 0x0 0x5e000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi
new file mode 100644
index 000000000000..3db8fcea6447
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Realtek RTD1920S Smallville EVB
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/thermal/thermal.h>
+#include "rtd1920.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:460800n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ protected_mem: protected-mem@50000 {
+ reg = <0x0 0x50000 0x0 0xbf0000>;
+ no-map;
+ };
+
+ metadata: metadata@c40000 {
+ reg = <0x0 0xc40000 0x0 0x3c4000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x0 0x0 0x20000000>;
+ size = <0x0 0x2000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ cpu_opps: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp800: opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <830000 830000 1100000>;
+ };
+
+ opp900: opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000 850000 1100000>;
+ };
+
+ opp1000: opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <870000 870000 1100000>;
+ };
+
+ opp1100: opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <890000 890000 1100000>;
+ };
+
+ opp1200: opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <910000 910000 1100000>;
+ };
+
+ opp1300: opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <930000 930000 1100000>;
+ };
+
+ opp1400: opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000 950000 1100000>;
+ };
+
+ opp1500: opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <970000 970000 1100000>;
+ };
+
+ opp1600: opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <990000 990000 1100000>;
+ opp-suspend;
+ };
+
+ opp1700: opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1010000 1010000 1100000>;
+ };
+
+ opp1800: opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1030000 1030000 1100000>;
+ };
+
+ opp1900: opp-1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1050000 1050000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opps>;
+ #cooling-cells = <2>;
+};
--
2.34.1On 27/01/2026 08:14, Yu-Chun Lin wrote:
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Earlier (I removed it from the context) nodes are not ordered according
to DTS coding style.
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + alignment = <0x0 0x400000>;
> + alloc-ranges = <0x0 0x0 0x0 0x20000000>;
> + size = <0x0 0x2000000>;
> + reusable;
> + linux,cma-default;
> + };
> + };
> +
> + cpu_opps: opp-table-cpu {
It is odd to see this on the board level. This really is SoC or (in your
case) SoC variant layer.
Same for other DTSI.
These two issues however are not critical and I did not see other
worrying things, so I would merge it.
Arnd:
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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