Convert the driver to use FIELD_PREP to increase readability.
This also fixes an issue that the SDPIF_CFGR_VDW_MASK was wrong,
which didn't have any effects as the only user in the driver
updates the other bits at the same time.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
sound/soc/rockchip/rockchip_spdif.c | 12 ++++-----
sound/soc/rockchip/rockchip_spdif.h | 53 +++++++++++++++++--------------------
2 files changed, 31 insertions(+), 34 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index 2c804d25c547..d0b9967cfe4d 100644
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -5,7 +5,7 @@
*
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
* Author: Jianqun <jay.xu@rock-chips.com>
- * Copyright (c) 2015 Collabora Ltd.
+ * Copyright (c) 2015-2026 Collabora Ltd.
* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
*/
@@ -159,7 +159,7 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
SPDIF_CFGR_CLK_DIV_MASK |
- SPDIF_CFGR_HALFWORD_ENABLE |
+ SPDIF_CFGR_HALFWORD_MASK |
SDPIF_CFGR_VDW_MASK |
SPDIF_CFGR_ADJ_MASK, val);
@@ -177,7 +177,7 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
- SPDIF_DMACR_TDE_ENABLE |
+ SPDIF_DMACR_TDE_MASK |
SPDIF_DMACR_TDL_MASK,
SPDIF_DMACR_TDE_ENABLE |
SPDIF_DMACR_TDL(16));
@@ -186,21 +186,21 @@ static int rk_spdif_trigger(struct snd_pcm_substream *substream,
return ret;
ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
- SPDIF_XFER_TXS_START,
+ SPDIF_XFER_TXS_MASK,
SPDIF_XFER_TXS_START);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
- SPDIF_DMACR_TDE_ENABLE,
+ SPDIF_DMACR_TDE_MASK,
SPDIF_DMACR_TDE_DISABLE);
if (ret != 0)
return ret;
ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
- SPDIF_XFER_TXS_START,
+ SPDIF_XFER_TXS_MASK,
SPDIF_XFER_TXS_STOP);
break;
default:
diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h
index b837b1f8d57f..ec33295e2512 100644
--- a/sound/soc/rockchip/rockchip_spdif.h
+++ b/sound/soc/rockchip/rockchip_spdif.h
@@ -2,7 +2,7 @@
/*
* ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
*
- * Copyright (c) 2015 Collabora Ltd.
+ * Copyright (c) 2015-2026 Collabora Ltd.
* Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
*/
@@ -13,53 +13,50 @@
* CFGR
* transfer configuration register
*/
-#define SPDIF_CFGR_CLK_DIV_SHIFT (16)
-#define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
-#define SPDIF_CFGR_CLK_DIV(x) ((x-1) << SPDIF_CFGR_CLK_DIV_SHIFT)
+#define SPDIF_CFGR_CLK_DIV_MASK GENMASK(23, 16)
+#define SPDIF_CFGR_CLK_DIV(x) FIELD_PREP(SPDIF_CFGR_CLK_DIV_MASK, x-1)
#define SPDIF_CFGR_CLR_MASK BIT(7)
-#define SPDIF_CFGR_CLR_EN BIT(7)
-#define SPDIF_CFGR_CLR_DIS 0
+#define SPDIF_CFGR_CLR_EN FIELD_PREP(SPDIF_CFGR_CLR_MASK, 1)
+#define SPDIF_CFGR_CLR_DIS FIELD_PREP(SPDIF_CFGR_CLR_MASK, 0)
#define SPDIF_CFGR_CSE_MASK BIT(6)
-#define SPDIF_CFGR_CSE_EN BIT(6)
-#define SPDIF_CFGR_CSE_DIS 0
+#define SPDIF_CFGR_CSE_EN FIELD_PREP(SPDIF_CFGR_CSE_MASK, 1)
+#define SPDIF_CFGR_CSE_DIS FIELD_PREP(SPDIF_CFGR_CSE_MASK, 0)
#define SPDIF_CFGR_ADJ_MASK BIT(3)
-#define SPDIF_CFGR_ADJ_LEFT_J BIT(3)
-#define SPDIF_CFGR_ADJ_RIGHT_J 0
+#define SPDIF_CFGR_ADJ_LEFT_J FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 1)
+#define SPDIF_CFGR_ADJ_RIGHT_J FIELD_PREP(SPDIF_CFGR_ADJ_MASK, 0)
-#define SPDIF_CFGR_HALFWORD_SHIFT 2
-#define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT)
-#define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)
+#define SPDIF_CFGR_HALFWORD_MASK BIT(2)
+#define SPDIF_CFGR_HALFWORD_DISABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 0)
+#define SPDIF_CFGR_HALFWORD_ENABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
-#define SPDIF_CFGR_VDW_SHIFT 0
-#define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
-#define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
+#define SDPIF_CFGR_VDW_MASK GENMASK(1, 0)
+#define SPDIF_CFGR_VDW(x) FIELD_PREP(SDPIF_CFGR_VDW_MASK, x)
-#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
-#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
-#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
+#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
+#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
+#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
/*
* DMACR
* DMA control register
*/
-#define SPDIF_DMACR_TDE_SHIFT 5
-#define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT)
-#define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT)
+#define SPDIF_DMACR_TDE_MASK BIT(5)
+#define SPDIF_DMACR_TDE_DISABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 0)
+#define SPDIF_DMACR_TDE_ENABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 1)
-#define SPDIF_DMACR_TDL_SHIFT 0
-#define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
-#define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
+#define SPDIF_DMACR_TDL_MASK GENMASK(4, 0)
+#define SPDIF_DMACR_TDL(x) FIELD_PREP(SPDIF_DMACR_TDL_MASK, x)
/*
* XFER
* Transfer control register
*/
-#define SPDIF_XFER_TXS_SHIFT 0
-#define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT)
-#define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT)
+#define SPDIF_XFER_TXS_MASK BIT(0)
+#define SPDIF_XFER_TXS_STOP FIELD_PREP(SPDIF_XFER_TXS_MASK, 0)
+#define SPDIF_XFER_TXS_START FIELD_PREP(SPDIF_XFER_TXS_MASK, 1)
#define SPDIF_CFGR (0x0000)
#define SPDIF_SDBLR (0x0004)
--
2.51.0Hi Sebastian,
kernel test robot noticed the following build errors:
[auto build test ERROR on 63804fed149a6750ffd28610c5c1c98cce6bd377]
url: https://github.com/intel-lab-lkp/linux/commits/Sebastian-Reichel/ASoC-rockchip-spdif-Use-device_get_match_data/20260128-001701
base: 63804fed149a6750ffd28610c5c1c98cce6bd377
patch link: https://lore.kernel.org/r/20260127-rockchip-spdif-cleanup-and-bsp-sync-v1-10-a7c547072bbb%40collabora.com
patch subject: [PATCH 10/10] ASoC: rockchip: spdif: Convert to FIELD_PREP
config: hexagon-randconfig-002-20260128 (https://download.01.org/0day-ci/archive/20260128/202601281701.vJDagmwh-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260128/202601281701.vJDagmwh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601281701.vJDagmwh-lkp@intel.com/
All errors (new ones prefixed by >>):
>> sound/soc/rockchip/rockchip_spdif.c:109:21: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
109 | unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
| ^
sound/soc/rockchip/rockchip_spdif.h:33:36: note: expanded from macro 'SPDIF_CFGR_HALFWORD_ENABLE'
33 | #define SPDIF_CFGR_HALFWORD_ENABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
| ^
sound/soc/rockchip/rockchip_spdif.c:182:7: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
182 | SPDIF_DMACR_TDE_ENABLE |
| ^
sound/soc/rockchip/rockchip_spdif.h:48:33: note: expanded from macro 'SPDIF_DMACR_TDE_ENABLE'
48 | #define SPDIF_DMACR_TDE_ENABLE FIELD_PREP(SPDIF_DMACR_TDE_MASK, 1)
| ^
2 errors generated.
vim +/FIELD_PREP +109 sound/soc/rockchip/rockchip_spdif.c
f874b80e157111 Sjoerd Simons 2015-10-08 102
f874b80e157111 Sjoerd Simons 2015-10-08 103 static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
f874b80e157111 Sjoerd Simons 2015-10-08 104 struct snd_pcm_hw_params *params,
f874b80e157111 Sjoerd Simons 2015-10-08 105 struct snd_soc_dai *dai)
f874b80e157111 Sjoerd Simons 2015-10-08 106 {
f874b80e157111 Sjoerd Simons 2015-10-08 107 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
b8e112b77e45b4 Sugar Zhang 2026-01-27 108 unsigned int mclk_rate = clk_get_rate(spdif->mclk);
f874b80e157111 Sjoerd Simons 2015-10-08 @109 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
9cd33c09d22fd1 Sugar Zhang 2026-01-27 110 int bmc, div, ret, i;
9cd33c09d22fd1 Sugar Zhang 2026-01-27 111 u16 *fc;
9cd33c09d22fd1 Sugar Zhang 2026-01-27 112 u8 cs[CS_BYTE];
9cd33c09d22fd1 Sugar Zhang 2026-01-27 113
9cd33c09d22fd1 Sugar Zhang 2026-01-27 114 ret = snd_pcm_create_iec958_consumer_hw_params(params, cs, sizeof(cs));
9cd33c09d22fd1 Sugar Zhang 2026-01-27 115 if (ret < 0)
9cd33c09d22fd1 Sugar Zhang 2026-01-27 116 return ret;
9cd33c09d22fd1 Sugar Zhang 2026-01-27 117
9cd33c09d22fd1 Sugar Zhang 2026-01-27 118 fc = (u16 *)cs;
9cd33c09d22fd1 Sugar Zhang 2026-01-27 119 for (i = 0; i < CS_BYTE / 2; i++)
9cd33c09d22fd1 Sugar Zhang 2026-01-27 120 regmap_write(spdif->regmap, SPDIF_CHNSRn(i), CS_FRAME(fc[i]));
9cd33c09d22fd1 Sugar Zhang 2026-01-27 121
9cd33c09d22fd1 Sugar Zhang 2026-01-27 122 regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CSE_MASK,
9cd33c09d22fd1 Sugar Zhang 2026-01-27 123 SPDIF_CFGR_CSE_EN);
f874b80e157111 Sjoerd Simons 2015-10-08 124
b8e112b77e45b4 Sugar Zhang 2026-01-27 125 /* bmc = 128fs */
b8e112b77e45b4 Sugar Zhang 2026-01-27 126 bmc = 128 * params_rate(params);
b8e112b77e45b4 Sugar Zhang 2026-01-27 127 div = DIV_ROUND_CLOSEST(mclk_rate, bmc);
b8e112b77e45b4 Sugar Zhang 2026-01-27 128 val |= SPDIF_CFGR_CLK_DIV(div);
f874b80e157111 Sjoerd Simons 2015-10-08 129
f874b80e157111 Sjoerd Simons 2015-10-08 130 switch (params_format(params)) {
f874b80e157111 Sjoerd Simons 2015-10-08 131 case SNDRV_PCM_FORMAT_S16_LE:
f874b80e157111 Sjoerd Simons 2015-10-08 132 val |= SPDIF_CFGR_VDW_16;
908589f3825713 Sugar Zhang 2026-01-27 133 val |= SPDIF_CFGR_ADJ_RIGHT_J;
f874b80e157111 Sjoerd Simons 2015-10-08 134 break;
f874b80e157111 Sjoerd Simons 2015-10-08 135 case SNDRV_PCM_FORMAT_S20_3LE:
f874b80e157111 Sjoerd Simons 2015-10-08 136 val |= SPDIF_CFGR_VDW_20;
908589f3825713 Sugar Zhang 2026-01-27 137 val |= SPDIF_CFGR_ADJ_RIGHT_J;
f874b80e157111 Sjoerd Simons 2015-10-08 138 break;
f874b80e157111 Sjoerd Simons 2015-10-08 139 case SNDRV_PCM_FORMAT_S24_LE:
f874b80e157111 Sjoerd Simons 2015-10-08 140 val |= SPDIF_CFGR_VDW_24;
908589f3825713 Sugar Zhang 2026-01-27 141 val |= SPDIF_CFGR_ADJ_RIGHT_J;
908589f3825713 Sugar Zhang 2026-01-27 142 break;
908589f3825713 Sugar Zhang 2026-01-27 143 case SNDRV_PCM_FORMAT_S32_LE:
908589f3825713 Sugar Zhang 2026-01-27 144 val |= SPDIF_CFGR_VDW_24;
908589f3825713 Sugar Zhang 2026-01-27 145 val |= SPDIF_CFGR_ADJ_LEFT_J;
f874b80e157111 Sjoerd Simons 2015-10-08 146 break;
f874b80e157111 Sjoerd Simons 2015-10-08 147 default:
f874b80e157111 Sjoerd Simons 2015-10-08 148 return -EINVAL;
f874b80e157111 Sjoerd Simons 2015-10-08 149 }
f874b80e157111 Sjoerd Simons 2015-10-08 150
908589f3825713 Sugar Zhang 2026-01-27 151 /*
908589f3825713 Sugar Zhang 2026-01-27 152 * clear MCLK domain logic before setting Fmclk and Fsdo to ensure
908589f3825713 Sugar Zhang 2026-01-27 153 * that switching between S16_LE and S32_LE audio does not result
908589f3825713 Sugar Zhang 2026-01-27 154 * in accidential channels swap.
908589f3825713 Sugar Zhang 2026-01-27 155 */
908589f3825713 Sugar Zhang 2026-01-27 156 regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLR_MASK,
908589f3825713 Sugar Zhang 2026-01-27 157 SPDIF_CFGR_CLR_EN);
908589f3825713 Sugar Zhang 2026-01-27 158 udelay(1);
908589f3825713 Sugar Zhang 2026-01-27 159
f874b80e157111 Sjoerd Simons 2015-10-08 160 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
acc8b9d117912c Sugar Zhang 2021-08-24 161 SPDIF_CFGR_CLK_DIV_MASK |
85c46be12ede08 Sebastian Reichel 2026-01-27 162 SPDIF_CFGR_HALFWORD_MASK |
908589f3825713 Sugar Zhang 2026-01-27 163 SDPIF_CFGR_VDW_MASK |
908589f3825713 Sugar Zhang 2026-01-27 164 SPDIF_CFGR_ADJ_MASK, val);
f874b80e157111 Sjoerd Simons 2015-10-08 165
f874b80e157111 Sjoerd Simons 2015-10-08 166 return ret;
f874b80e157111 Sjoerd Simons 2015-10-08 167 }
f874b80e157111 Sjoerd Simons 2015-10-08 168
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Sebastian,
kernel test robot noticed the following build errors:
[auto build test ERROR on 63804fed149a6750ffd28610c5c1c98cce6bd377]
url: https://github.com/intel-lab-lkp/linux/commits/Sebastian-Reichel/ASoC-rockchip-spdif-Use-device_get_match_data/20260128-001701
base: 63804fed149a6750ffd28610c5c1c98cce6bd377
patch link: https://lore.kernel.org/r/20260127-rockchip-spdif-cleanup-and-bsp-sync-v1-10-a7c547072bbb%40collabora.com
patch subject: [PATCH 10/10] ASoC: rockchip: spdif: Convert to FIELD_PREP
config: sh-allyesconfig (https://download.01.org/0day-ci/archive/20260128/202601281116.z12yhNfr-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260128/202601281116.z12yhNfr-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601281116.z12yhNfr-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from sound/soc/rockchip/rockchip_spdif.c:22:
sound/soc/rockchip/rockchip_spdif.c: In function 'rk_spdif_hw_params':
>> sound/soc/rockchip/rockchip_spdif.h:33:41: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
33 | #define SPDIF_CFGR_HALFWORD_ENABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
| ^~~~~~~~~~
sound/soc/rockchip/rockchip_spdif.c:109:28: note: in expansion of macro 'SPDIF_CFGR_HALFWORD_ENABLE'
109 | unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/FIELD_PREP +33 sound/soc/rockchip/rockchip_spdif.h
30
31 #define SPDIF_CFGR_HALFWORD_MASK BIT(2)
32 #define SPDIF_CFGR_HALFWORD_DISABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 0)
> 33 #define SPDIF_CFGR_HALFWORD_ENABLE FIELD_PREP(SPDIF_CFGR_HALFWORD_MASK, 1)
34
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
© 2016 - 2026 Red Hat, Inc.