Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm
Mahua platform.
Mahua is a derivative of the Glymur SoC. Many interconnect nodes are
identical and continue to use Glymur fallback compatibles. Mahua
introduces SoC-specific configurations and topologies for several
NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs.
This updates the existing Glymur yaml schema to include Mahua-specific
compatible strings, using two-cell "fallback" compatibles wherever
the hardware is identical with Glymur.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
.../bindings/interconnect/qcom,glymur-rpmh.yaml | 132 +++++++++++++++++----
1 file changed, 109 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
index d55a7bcf5591eea79c173a12b12c659321ca3c2e..723ae547ae06073b7fa93dc7a94f33336068519b 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR
+title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs
maintainers:
- Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
@@ -21,28 +21,98 @@ description: |
properties:
compatible:
- enum:
- - qcom,glymur-aggre1-noc
- - qcom,glymur-aggre2-noc
- - qcom,glymur-aggre3-noc
- - qcom,glymur-aggre4-noc
- - qcom,glymur-clk-virt
- - qcom,glymur-cnoc-cfg
- - qcom,glymur-cnoc-main
- - qcom,glymur-hscnoc
- - qcom,glymur-lpass-ag-noc
- - qcom,glymur-lpass-lpiaon-noc
- - qcom,glymur-lpass-lpicx-noc
- - qcom,glymur-mc-virt
- - qcom,glymur-mmss-noc
- - qcom,glymur-nsinoc
- - qcom,glymur-nsp-noc
- - qcom,glymur-oobm-ss-noc
- - qcom,glymur-pcie-east-anoc
- - qcom,glymur-pcie-east-slv-noc
- - qcom,glymur-pcie-west-anoc
- - qcom,glymur-pcie-west-slv-noc
- - qcom,glymur-system-noc
+ oneOf:
+ - items:
+ - enum:
+ - qcom,mahua-clk-virt
+ - const: qcom,glymur-clk-virt
+ - items:
+ - enum:
+ - qcom,mahua-cnoc-main
+ - const: qcom,glymur-cnoc-main
+ - items:
+ - enum:
+ - qcom,mahua-system-noc
+ - const: qcom,glymur-system-noc
+ - items:
+ - enum:
+ - qcom,mahua-pcie-east-anoc
+ - const: qcom,glymur-pcie-east-anoc
+ - items:
+ - enum:
+ - qcom,mahua-aggre1-noc
+ - const: qcom,glymur-aggre1-noc
+ - items:
+ - enum:
+ - qcom,mahua-aggre2-noc
+ - const: qcom,glymur-aggre2-noc
+ - items:
+ - enum:
+ - qcom,mahua-aggre3-noc
+ - const: qcom,glymur-aggre3-noc
+ - items:
+ - enum:
+ - qcom,mahua-aggre4-noc
+ - const: qcom,glymur-aggre4-noc
+ - items:
+ - enum:
+ - qcom,mahua-mmss-noc
+ - const: qcom,glymur-mmss-noc
+ - items:
+ - enum:
+ - qcom,mahua-pcie-east-slv-noc
+ - const: qcom,glymur-pcie-east-slv-noc
+ - items:
+ - enum:
+ - qcom,mahua-lpass-lpiaon-noc
+ - const: qcom,glymur-lpass-lpiaon-noc
+ - items:
+ - enum:
+ - qcom,mahua-lpass-lpicx-noc
+ - const: qcom,glymur-lpass-lpicx-noc
+ - items:
+ - enum:
+ - qcom,mahua-lpass-ag-noc
+ - const: qcom,glymur-lpass-ag-noc
+ - items:
+ - enum:
+ - qcom,mahua-nsinoc
+ - const: qcom,glymur-nsinoc
+ - items:
+ - enum:
+ - qcom,mahua-oobm-ss-noc
+ - const: qcom,glymur-oobm-ss-noc
+ - items:
+ - enum:
+ - qcom,mahua-nsp-noc
+ - const: qcom,glymur-nsp-noc
+ - enum:
+ - qcom,glymur-aggre1-noc
+ - qcom,glymur-aggre2-noc
+ - qcom,glymur-aggre3-noc
+ - qcom,glymur-aggre4-noc
+ - qcom,glymur-clk-virt
+ - qcom,glymur-cnoc-cfg
+ - qcom,glymur-cnoc-main
+ - qcom,glymur-hscnoc
+ - qcom,glymur-lpass-ag-noc
+ - qcom,glymur-lpass-lpiaon-noc
+ - qcom,glymur-lpass-lpicx-noc
+ - qcom,glymur-mc-virt
+ - qcom,glymur-mmss-noc
+ - qcom,glymur-nsinoc
+ - qcom,glymur-nsp-noc
+ - qcom,glymur-oobm-ss-noc
+ - qcom,glymur-pcie-east-anoc
+ - qcom,glymur-pcie-east-slv-noc
+ - qcom,glymur-pcie-west-anoc
+ - qcom,glymur-pcie-west-slv-noc
+ - qcom,glymur-system-noc
+ - qcom,mahua-mc-virt
+ - qcom,mahua-cnoc-cfg
+ - qcom,mahua-pcie-west-anoc
+ - qcom,mahua-pcie-west-slv-noc
+ - qcom,mahua-hscnoc
reg:
maxItems: 1
@@ -63,6 +133,7 @@ allOf:
enum:
- qcom,glymur-clk-virt
- qcom,glymur-mc-virt
+ - qcom,mahua-mc-virt
then:
properties:
reg: false
@@ -85,6 +156,20 @@ allOf:
- description: aggre PCIE_4 WEST AXI clock
- description: aggre PCIE_6 WEST AXI clock
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,mahua-pcie-west-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre PCIE_3B WEST AXI clock
+ - description: aggre PCIE_4 WEST AXI clock
+ - description: aggre PCIE_6 WEST AXI clock
+
- if:
properties:
compatible:
@@ -132,6 +217,7 @@ allOf:
contains:
enum:
- qcom,glymur-pcie-west-anoc
+ - qcom,mahua-pcie-west-anoc
- qcom,glymur-pcie-east-anoc
- qcom,glymur-aggre2-noc
- qcom,glymur-aggre4-noc
--
2.43.0On Tue, Jan 27, 2026 at 03:22:06AM +0000, Raviteja Laggyshetty wrote: > + oneOf: > + - items: > + - enum: > + - qcom,mahua-clk-virt > + - const: qcom,glymur-clk-virt > + - items: > + - enum: > + - qcom,mahua-cnoc-main > + - const: qcom,glymur-cnoc-main > + - items: > + - enum: > + - qcom,mahua-system-noc > + - const: qcom,glymur-system-noc > + - items: > + - enum: > + - qcom,mahua-pcie-east-anoc > + - const: qcom,glymur-pcie-east-anoc > + - items: > + - enum: > + - qcom,mahua-aggre1-noc > + - const: qcom,glymur-aggre1-noc All these "items" blocks should be sorted by the fallback, so qcom,glymur-aggre1-noc is before qcom,glymur-clk-virt. > + - items: > + - enum: > + - qcom,mahua-aggre2-noc > + - const: qcom,glymur-aggre2-noc > + - items: > + - enum: > + - qcom,mahua-aggre3-noc > + - const: qcom,glymur-aggre3-noc > + - items: > + - enum: > + - qcom,mahua-aggre4-noc > + - const: qcom,glymur-aggre4-noc > + - items: > + - enum: > + - qcom,mahua-mmss-noc > + - const: qcom,glymur-mmss-noc > + - items: > + - enum: > + - qcom,mahua-pcie-east-slv-noc > + - const: qcom,glymur-pcie-east-slv-noc > + - items: > + - enum: > + - qcom,mahua-lpass-lpiaon-noc > + - const: qcom,glymur-lpass-lpiaon-noc > + - items: > + - enum: > + - qcom,mahua-lpass-lpicx-noc > + - const: qcom,glymur-lpass-lpicx-noc > + - items: > + - enum: > + - qcom,mahua-lpass-ag-noc > + - const: qcom,glymur-lpass-ag-noc > + - items: > + - enum: > + - qcom,mahua-nsinoc > + - const: qcom,glymur-nsinoc > + - items: > + - enum: > + - qcom,mahua-oobm-ss-noc > + - const: qcom,glymur-oobm-ss-noc > + - items: > + - enum: > + - qcom,mahua-nsp-noc > + - const: qcom,glymur-nsp-noc > + - enum: > + - qcom,glymur-aggre1-noc > + - qcom,glymur-aggre2-noc > + - qcom,glymur-aggre3-noc > + - qcom,glymur-aggre4-noc > + - qcom,glymur-clk-virt > + - qcom,glymur-cnoc-cfg > + - qcom,glymur-cnoc-main > + - qcom,glymur-hscnoc > + - qcom,glymur-lpass-ag-noc > + - qcom,glymur-lpass-lpiaon-noc > + - qcom,glymur-lpass-lpicx-noc > + - qcom,glymur-mc-virt > + - qcom,glymur-mmss-noc > + - qcom,glymur-nsinoc > + - qcom,glymur-nsp-noc > + - qcom,glymur-oobm-ss-noc > + - qcom,glymur-pcie-east-anoc > + - qcom,glymur-pcie-east-slv-noc > + - qcom,glymur-pcie-west-anoc > + - qcom,glymur-pcie-west-slv-noc > + - qcom,glymur-system-noc > + - qcom,mahua-mc-virt > + - qcom,mahua-cnoc-cfg > + - qcom,mahua-pcie-west-anoc > + - qcom,mahua-pcie-west-slv-noc > + - qcom,mahua-hscnoc > > reg: > maxItems: 1 > @@ -63,6 +133,7 @@ allOf: > enum: > - qcom,glymur-clk-virt > - qcom,glymur-mc-virt > + - qcom,mahua-mc-virt > then: > properties: > reg: false > @@ -85,6 +156,20 @@ allOf: > - description: aggre PCIE_4 WEST AXI clock > - description: aggre PCIE_6 WEST AXI clock > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,mahua-pcie-west-anoc > + then: > + properties: > + clocks: > + items: > + - description: aggre PCIE_3B WEST AXI clock > + - description: aggre PCIE_4 WEST AXI clock > + - description: aggre PCIE_6 WEST AXI clock > + > - if: > properties: > compatible: > @@ -132,6 +217,7 @@ allOf: > contains: > enum: > - qcom,glymur-pcie-west-anoc > + - qcom,mahua-pcie-west-anoc Messed sorting. I don't get why such trivialities are still happening... > - qcom,glymur-pcie-east-anoc > - qcom,glymur-aggre2-noc > - qcom,glymur-aggre4-noc > > -- > 2.43.0 >
On 2/5/2026 5:25 PM, Krzysztof Kozlowski wrote: > On Tue, Jan 27, 2026 at 03:22:06AM +0000, Raviteja Laggyshetty wrote: >> + oneOf: >> + - items: >> + - enum: >> + - qcom,mahua-clk-virt >> + - const: qcom,glymur-clk-virt >> + - items: >> + - enum: >> + - qcom,mahua-cnoc-main >> + - const: qcom,glymur-cnoc-main >> + - items: >> + - enum: >> + - qcom,mahua-system-noc >> + - const: qcom,glymur-system-noc >> + - items: >> + - enum: >> + - qcom,mahua-pcie-east-anoc >> + - const: qcom,glymur-pcie-east-anoc >> + - items: >> + - enum: >> + - qcom,mahua-aggre1-noc >> + - const: qcom,glymur-aggre1-noc > > All these "items" blocks should be sorted by the fallback, so > qcom,glymur-aggre1-noc is before qcom,glymur-clk-virt. Will fix the sorting and post the next revision. > > >> + - items: >> + - enum: >> + - qcom,mahua-aggre2-noc >> + - const: qcom,glymur-aggre2-noc >> + - items: >> + - enum: >> + - qcom,mahua-aggre3-noc >> + - const: qcom,glymur-aggre3-noc >> + - items: >> + - enum: >> + - qcom,mahua-aggre4-noc >> + - const: qcom,glymur-aggre4-noc >> + - items: >> + - enum: >> + - qcom,mahua-mmss-noc >> + - const: qcom,glymur-mmss-noc >> + - items: >> + - enum: >> + - qcom,mahua-pcie-east-slv-noc >> + - const: qcom,glymur-pcie-east-slv-noc >> + - items: >> + - enum: >> + - qcom,mahua-lpass-lpiaon-noc >> + - const: qcom,glymur-lpass-lpiaon-noc >> + - items: >> + - enum: >> + - qcom,mahua-lpass-lpicx-noc >> + - const: qcom,glymur-lpass-lpicx-noc >> + - items: >> + - enum: >> + - qcom,mahua-lpass-ag-noc >> + - const: qcom,glymur-lpass-ag-noc >> + - items: >> + - enum: >> + - qcom,mahua-nsinoc >> + - const: qcom,glymur-nsinoc >> + - items: >> + - enum: >> + - qcom,mahua-oobm-ss-noc >> + - const: qcom,glymur-oobm-ss-noc >> + - items: >> + - enum: >> + - qcom,mahua-nsp-noc >> + - const: qcom,glymur-nsp-noc >> + - enum: >> + - qcom,glymur-aggre1-noc >> + - qcom,glymur-aggre2-noc >> + - qcom,glymur-aggre3-noc >> + - qcom,glymur-aggre4-noc >> + - qcom,glymur-clk-virt >> + - qcom,glymur-cnoc-cfg >> + - qcom,glymur-cnoc-main >> + - qcom,glymur-hscnoc >> + - qcom,glymur-lpass-ag-noc >> + - qcom,glymur-lpass-lpiaon-noc >> + - qcom,glymur-lpass-lpicx-noc >> + - qcom,glymur-mc-virt >> + - qcom,glymur-mmss-noc >> + - qcom,glymur-nsinoc >> + - qcom,glymur-nsp-noc >> + - qcom,glymur-oobm-ss-noc >> + - qcom,glymur-pcie-east-anoc >> + - qcom,glymur-pcie-east-slv-noc >> + - qcom,glymur-pcie-west-anoc >> + - qcom,glymur-pcie-west-slv-noc >> + - qcom,glymur-system-noc >> + - qcom,mahua-mc-virt >> + - qcom,mahua-cnoc-cfg >> + - qcom,mahua-pcie-west-anoc >> + - qcom,mahua-pcie-west-slv-noc >> + - qcom,mahua-hscnoc >> >> reg: >> maxItems: 1 >> @@ -63,6 +133,7 @@ allOf: >> enum: >> - qcom,glymur-clk-virt >> - qcom,glymur-mc-virt >> + - qcom,mahua-mc-virt >> then: >> properties: >> reg: false >> @@ -85,6 +156,20 @@ allOf: >> - description: aggre PCIE_4 WEST AXI clock >> - description: aggre PCIE_6 WEST AXI clock >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,mahua-pcie-west-anoc >> + then: >> + properties: >> + clocks: >> + items: >> + - description: aggre PCIE_3B WEST AXI clock >> + - description: aggre PCIE_4 WEST AXI clock >> + - description: aggre PCIE_6 WEST AXI clock >> + >> - if: >> properties: >> compatible: >> @@ -132,6 +217,7 @@ allOf: >> contains: >> enum: >> - qcom,glymur-pcie-west-anoc >> + - qcom,mahua-pcie-west-anoc > > Messed sorting. I don't get why such trivialities are still happening... I will fix the sorting here as well and won't let this happen in future patches. > >> - qcom,glymur-pcie-east-anoc >> - qcom,glymur-aggre2-noc >> - qcom,glymur-aggre4-noc >> >> -- >> 2.43.0 >>
On 1/27/26 4:22 AM, Raviteja Laggyshetty wrote: > Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm > Mahua platform. > > Mahua is a derivative of the Glymur SoC. Many interconnect nodes are > identical and continue to use Glymur fallback compatibles. Mahua > introduces SoC-specific configurations and topologies for several > NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs. > This updates the existing Glymur yaml schema to include Mahua-specific > compatible strings, using two-cell "fallback" compatibles wherever > the hardware is identical with Glymur. > > Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> > Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> > --- Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
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