Add the TCSR clock controller that provides the refclks on Eliza
platform for PCIe, USB and UFS subsystems.
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 8 +++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/tcsrcc-eliza.c | 144 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 153 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index edac919d3aa2..dce21e33e366 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -28,6 +28,14 @@ config CLK_ELIZA_GCC
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
+config CLK_ELIZA_TCSRCC
+ tristate "Eliza TCSR Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select QCOM_GDSC
+ help
+ Support for the TCSR clock controller on Eliza devices.
+ Say Y if you want to use peripheral devices such as USB/PCIe/UFS.
+
config CLK_GLYMUR_DISPCC
tristate "GLYMUR Display Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6ec63a5d4363..d2bbaaada826 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_ELIZA_GCC) += gcc-eliza.o
+obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
diff --git a/drivers/clk/qcom/tcsrcc-eliza.c b/drivers/clk/qcom/tcsrcc-eliza.c
new file mode 100644
index 000000000000..e01c40341d40
--- /dev/null
+++ b/drivers/clk/qcom/tcsrcc-eliza.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,eliza-tcsr.h>
+
+#include "clk-branch.h"
+#include "clk-regmap.h"
+#include "common.h"
+
+enum {
+ DT_BI_TCXO_PAD,
+};
+
+static struct clk_branch tcsr_pcie_0_clkref_en = {
+ .halt_reg = 0x0,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_pcie_0_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_ufs_clkref_en = {
+ .halt_reg = 0x8,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_ufs_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb2_clkref_en = {
+ .halt_reg = 0x4,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb2_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch tcsr_usb3_clkref_en = {
+ .halt_reg = 0x10,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x10,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "tcsr_usb3_clkref_en",
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO_PAD,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *tcsr_cc_eliza_clocks[] = {
+ [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
+ [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
+ [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
+ [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
+};
+
+static const struct regmap_config tcsr_cc_eliza_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1c,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc tcsr_cc_eliza_desc = {
+ .config = &tcsr_cc_eliza_regmap_config,
+ .clks = tcsr_cc_eliza_clocks,
+ .num_clks = ARRAY_SIZE(tcsr_cc_eliza_clocks),
+};
+
+static const struct of_device_id tcsr_cc_eliza_match_table[] = {
+ { .compatible = "qcom,eliza-tcsr" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tcsr_cc_eliza_match_table);
+
+static int tcsr_cc_eliza_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &tcsr_cc_eliza_desc);
+}
+
+static struct platform_driver tcsr_cc_eliza_driver = {
+ .probe = tcsr_cc_eliza_probe,
+ .driver = {
+ .name = "tcsr_cc-eliza",
+ .of_match_table = tcsr_cc_eliza_match_table,
+ },
+};
+
+static int __init tcsr_cc_eliza_init(void)
+{
+ return platform_driver_register(&tcsr_cc_eliza_driver);
+}
+subsys_initcall(tcsr_cc_eliza_init);
+
+static void __exit tcsr_cc_eliza_exit(void)
+{
+ platform_driver_unregister(&tcsr_cc_eliza_driver);
+}
+module_exit(tcsr_cc_eliza_exit);
+
+MODULE_DESCRIPTION("QTI TCSR_CC Eliza Driver");
+MODULE_LICENSE("GPL");
--
2.48.1On 1/27/26 4:03 PM, Abel Vesa wrote:
> Add the TCSR clock controller that provides the refclks on Eliza
> platform for PCIe, USB and UFS subsystems.
>
> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
[...]
> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> @@ -0,0 +1,144 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> +
> +#include "clk-branch.h"
> +#include "clk-regmap.h"
> +#include "common.h"
> +
> +enum {
> + DT_BI_TCXO_PAD,
> +};
> +
> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> + .halt_reg = 0x0,
These regs certainly aren't at +0x0 to what we normally expect to
be the start of the TCSR node
[...]
> +static struct clk_regmap *tcsr_cc_eliza_clocks[] = {
> + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
> + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
> + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
> + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
I don't think this list is complete
Konrad
On 26-01-28 11:34:49, Konrad Dybcio wrote:
> On 1/27/26 4:03 PM, Abel Vesa wrote:
> > Add the TCSR clock controller that provides the refclks on Eliza
> > platform for PCIe, USB and UFS subsystems.
> >
> > Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > ---
>
> [...]
>
> > +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> > @@ -0,0 +1,144 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> > +
> > +#include "clk-branch.h"
> > +#include "clk-regmap.h"
> > +#include "common.h"
> > +
> > +enum {
> > + DT_BI_TCXO_PAD,
> > +};
> > +
> > +static struct clk_branch tcsr_pcie_0_clkref_en = {
> > + .halt_reg = 0x0,
>
> These regs certainly aren't at +0x0 to what we normally expect to
> be the start of the TCSR node
They are if we add the TCSR node with reg range starting at 0x1fbf000.
>
> [...]
>
> > +static struct clk_regmap *tcsr_cc_eliza_clocks[] = {
> > + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
> > + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
> > + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
> > + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
>
> I don't think this list is complete
Yep, missing the pcie_0 and hdmi. Will add.
On 1/28/26 3:10 PM, Abel Vesa wrote:
> On 26-01-28 11:34:49, Konrad Dybcio wrote:
>> On 1/27/26 4:03 PM, Abel Vesa wrote:
>>> Add the TCSR clock controller that provides the refclks on Eliza
>>> platform for PCIe, USB and UFS subsystems.
>>>
>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
>>> @@ -0,0 +1,144 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>>> + */
>>> +
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/mod_devicetable.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
>>> +
>>> +#include "clk-branch.h"
>>> +#include "clk-regmap.h"
>>> +#include "common.h"
>>> +
>>> +enum {
>>> + DT_BI_TCXO_PAD,
>>> +};
>>> +
>>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
>>> + .halt_reg = 0x0,
>>
>> These regs certainly aren't at +0x0 to what we normally expect to
>> be the start of the TCSR node
>
> They are if we add the TCSR node with reg range starting at 0x1fbf000.
"if we take the wrong base, the wrong offset is right" ;)
The docs for Eliza don't have the nice separation like on e.g. Hamoa,
but 0x01fc0000 is what we generally agreed upon to be "tcsr".
The registers that first appear in that region are the same as on Hamoa,
and so is the address, so let's continue that tradition
Konrad
On 26-01-30 10:43:44, Konrad Dybcio wrote:
> On 1/28/26 3:10 PM, Abel Vesa wrote:
> > On 26-01-28 11:34:49, Konrad Dybcio wrote:
> >> On 1/27/26 4:03 PM, Abel Vesa wrote:
> >>> Add the TCSR clock controller that provides the refclks on Eliza
> >>> platform for PCIe, USB and UFS subsystems.
> >>>
> >>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> >>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> >>> @@ -0,0 +1,144 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-only
> >>> +/*
> >>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >>> + */
> >>> +
> >>> +#include <linux/clk-provider.h>
> >>> +#include <linux/mod_devicetable.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/platform_device.h>
> >>> +#include <linux/regmap.h>
> >>> +
> >>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> >>> +
> >>> +#include "clk-branch.h"
> >>> +#include "clk-regmap.h"
> >>> +#include "common.h"
> >>> +
> >>> +enum {
> >>> + DT_BI_TCXO_PAD,
> >>> +};
> >>> +
> >>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> >>> + .halt_reg = 0x0,
> >>
> >> These regs certainly aren't at +0x0 to what we normally expect to
> >> be the start of the TCSR node
> >
> > They are if we add the TCSR node with reg range starting at 0x1fbf000.
>
> "if we take the wrong base, the wrong offset is right" ;)
>
> The docs for Eliza don't have the nice separation like on e.g. Hamoa,
> but 0x01fc0000 is what we generally agreed upon to be "tcsr".
>
> The registers that first appear in that region are the same as on Hamoa,
> and so is the address, so let's continue that tradition
Sure.
On 26-01-30 22:40:32, Abel Vesa wrote:
> On 26-01-30 10:43:44, Konrad Dybcio wrote:
> > On 1/28/26 3:10 PM, Abel Vesa wrote:
> > > On 26-01-28 11:34:49, Konrad Dybcio wrote:
> > >> On 1/27/26 4:03 PM, Abel Vesa wrote:
> > >>> Add the TCSR clock controller that provides the refclks on Eliza
> > >>> platform for PCIe, USB and UFS subsystems.
> > >>>
> > >>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > >>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > >>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > >>> ---
> > >>
> > >> [...]
> > >>
> > >>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> > >>> @@ -0,0 +1,144 @@
> > >>> +// SPDX-License-Identifier: GPL-2.0-only
> > >>> +/*
> > >>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > >>> + */
> > >>> +
> > >>> +#include <linux/clk-provider.h>
> > >>> +#include <linux/mod_devicetable.h>
> > >>> +#include <linux/module.h>
> > >>> +#include <linux/of.h>
> > >>> +#include <linux/platform_device.h>
> > >>> +#include <linux/regmap.h>
> > >>> +
> > >>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> > >>> +
> > >>> +#include "clk-branch.h"
> > >>> +#include "clk-regmap.h"
> > >>> +#include "common.h"
> > >>> +
> > >>> +enum {
> > >>> + DT_BI_TCXO_PAD,
> > >>> +};
> > >>> +
> > >>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> > >>> + .halt_reg = 0x0,
> > >>
> > >> These regs certainly aren't at +0x0 to what we normally expect to
> > >> be the start of the TCSR node
> > >
> > > They are if we add the TCSR node with reg range starting at 0x1fbf000.
> >
> > "if we take the wrong base, the wrong offset is right" ;)
> >
> > The docs for Eliza don't have the nice separation like on e.g. Hamoa,
> > but 0x01fc0000 is what we generally agreed upon to be "tcsr".
> >
> > The registers that first appear in that region are the same as on Hamoa,
> > and so is the address, so let's continue that tradition
Actually, the 0x1fbf000 is the right base address.
TCSR mutex starts at 0x1f40000, and everything between 0x1fb2000 and 0xfbf000
doesn't really look like they belong in a clock controller.
On 2/2/26 9:53 PM, Abel Vesa wrote:
> On 26-01-30 22:40:32, Abel Vesa wrote:
>> On 26-01-30 10:43:44, Konrad Dybcio wrote:
>>> On 1/28/26 3:10 PM, Abel Vesa wrote:
>>>> On 26-01-28 11:34:49, Konrad Dybcio wrote:
>>>>> On 1/27/26 4:03 PM, Abel Vesa wrote:
>>>>>> Add the TCSR clock controller that provides the refclks on Eliza
>>>>>> platform for PCIe, USB and UFS subsystems.
>>>>>>
>>>>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>>>> ---
>>>>>
>>>>> [...]
>>>>>
>>>>>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
>>>>>> @@ -0,0 +1,144 @@
>>>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>>>> +/*
>>>>>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>>>>>> + */
>>>>>> +
>>>>>> +#include <linux/clk-provider.h>
>>>>>> +#include <linux/mod_devicetable.h>
>>>>>> +#include <linux/module.h>
>>>>>> +#include <linux/of.h>
>>>>>> +#include <linux/platform_device.h>
>>>>>> +#include <linux/regmap.h>
>>>>>> +
>>>>>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
>>>>>> +
>>>>>> +#include "clk-branch.h"
>>>>>> +#include "clk-regmap.h"
>>>>>> +#include "common.h"
>>>>>> +
>>>>>> +enum {
>>>>>> + DT_BI_TCXO_PAD,
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
>>>>>> + .halt_reg = 0x0,
>>>>>
>>>>> These regs certainly aren't at +0x0 to what we normally expect to
>>>>> be the start of the TCSR node
>>>>
>>>> They are if we add the TCSR node with reg range starting at 0x1fbf000.
>>>
>>> "if we take the wrong base, the wrong offset is right" ;)
>>>
>>> The docs for Eliza don't have the nice separation like on e.g. Hamoa,
>>> but 0x01fc0000 is what we generally agreed upon to be "tcsr".
>>>
>>> The registers that first appear in that region are the same as on Hamoa,
>>> and so is the address, so let's continue that tradition
>
> Actually, the 0x1fbf000 is the right base address.
Actually, I think it's 0x1fb_2000 ;)
> TCSR mutex starts at 0x1f40000, and everything between 0x1fb2000 and 0xfbf000
> doesn't really look like they belong in a clock controller.
Correct, and that's because TCSR is not a clock controller.
Konrad
On 26-02-04 13:36:57, Konrad Dybcio wrote:
> On 2/2/26 9:53 PM, Abel Vesa wrote:
> > On 26-01-30 22:40:32, Abel Vesa wrote:
> >> On 26-01-30 10:43:44, Konrad Dybcio wrote:
> >>> On 1/28/26 3:10 PM, Abel Vesa wrote:
> >>>> On 26-01-28 11:34:49, Konrad Dybcio wrote:
> >>>>> On 1/27/26 4:03 PM, Abel Vesa wrote:
> >>>>>> Add the TCSR clock controller that provides the refclks on Eliza
> >>>>>> platform for PCIe, USB and UFS subsystems.
> >>>>>>
> >>>>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> >>>>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> >>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >>>>>> ---
> >>>>>
> >>>>> [...]
> >>>>>
> >>>>>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> >>>>>> @@ -0,0 +1,144 @@
> >>>>>> +// SPDX-License-Identifier: GPL-2.0-only
> >>>>>> +/*
> >>>>>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >>>>>> + */
> >>>>>> +
> >>>>>> +#include <linux/clk-provider.h>
> >>>>>> +#include <linux/mod_devicetable.h>
> >>>>>> +#include <linux/module.h>
> >>>>>> +#include <linux/of.h>
> >>>>>> +#include <linux/platform_device.h>
> >>>>>> +#include <linux/regmap.h>
> >>>>>> +
> >>>>>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> >>>>>> +
> >>>>>> +#include "clk-branch.h"
> >>>>>> +#include "clk-regmap.h"
> >>>>>> +#include "common.h"
> >>>>>> +
> >>>>>> +enum {
> >>>>>> + DT_BI_TCXO_PAD,
> >>>>>> +};
> >>>>>> +
> >>>>>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> >>>>>> + .halt_reg = 0x0,
> >>>>>
> >>>>> These regs certainly aren't at +0x0 to what we normally expect to
> >>>>> be the start of the TCSR node
> >>>>
> >>>> They are if we add the TCSR node with reg range starting at 0x1fbf000.
> >>>
> >>> "if we take the wrong base, the wrong offset is right" ;)
> >>>
> >>> The docs for Eliza don't have the nice separation like on e.g. Hamoa,
> >>> but 0x01fc0000 is what we generally agreed upon to be "tcsr".
> >>>
> >>> The registers that first appear in that region are the same as on Hamoa,
> >>> and so is the address, so let's continue that tradition
> >
> > Actually, the 0x1fbf000 is the right base address.
>
> Actually, I think it's 0x1fb_2000 ;)
As discussed off-list, using 0x1fb_2000 would include regs that Kaanapali for example
doesn't. So will use the 0x1fc_0000.
>
> > TCSR mutex starts at 0x1f40000, and everything between 0x1fb2000 and 0xfbf000
> > doesn't really look like they belong in a clock controller.
>
> Correct, and that's because TCSR is not a clock controller.
Correct, but as agreed off-list, for consistency reasons w.r.t. other SoCs,
it should not include that gap.
Thanks,
Abel
On 26-02-06 14:50:44, Abel Vesa wrote:
> On 26-02-04 13:36:57, Konrad Dybcio wrote:
> > On 2/2/26 9:53 PM, Abel Vesa wrote:
> > > On 26-01-30 22:40:32, Abel Vesa wrote:
> > >> On 26-01-30 10:43:44, Konrad Dybcio wrote:
> > >>> On 1/28/26 3:10 PM, Abel Vesa wrote:
> > >>>> On 26-01-28 11:34:49, Konrad Dybcio wrote:
> > >>>>> On 1/27/26 4:03 PM, Abel Vesa wrote:
> > >>>>>> Add the TCSR clock controller that provides the refclks on Eliza
> > >>>>>> platform for PCIe, USB and UFS subsystems.
> > >>>>>>
> > >>>>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > >>>>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> > >>>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> > >>>>>> ---
> > >>>>>
> > >>>>> [...]
> > >>>>>
> > >>>>>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> > >>>>>> @@ -0,0 +1,144 @@
> > >>>>>> +// SPDX-License-Identifier: GPL-2.0-only
> > >>>>>> +/*
> > >>>>>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > >>>>>> + */
> > >>>>>> +
> > >>>>>> +#include <linux/clk-provider.h>
> > >>>>>> +#include <linux/mod_devicetable.h>
> > >>>>>> +#include <linux/module.h>
> > >>>>>> +#include <linux/of.h>
> > >>>>>> +#include <linux/platform_device.h>
> > >>>>>> +#include <linux/regmap.h>
> > >>>>>> +
> > >>>>>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> > >>>>>> +
> > >>>>>> +#include "clk-branch.h"
> > >>>>>> +#include "clk-regmap.h"
> > >>>>>> +#include "common.h"
> > >>>>>> +
> > >>>>>> +enum {
> > >>>>>> + DT_BI_TCXO_PAD,
> > >>>>>> +};
> > >>>>>> +
> > >>>>>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> > >>>>>> + .halt_reg = 0x0,
> > >>>>>
> > >>>>> These regs certainly aren't at +0x0 to what we normally expect to
> > >>>>> be the start of the TCSR node
> > >>>>
> > >>>> They are if we add the TCSR node with reg range starting at 0x1fbf000.
> > >>>
> > >>> "if we take the wrong base, the wrong offset is right" ;)
> > >>>
> > >>> The docs for Eliza don't have the nice separation like on e.g. Hamoa,
> > >>> but 0x01fc0000 is what we generally agreed upon to be "tcsr".
> > >>>
> > >>> The registers that first appear in that region are the same as on Hamoa,
> > >>> and so is the address, so let's continue that tradition
> > >
> > > Actually, the 0x1fbf000 is the right base address.
> >
> > Actually, I think it's 0x1fb_2000 ;)
>
> As discussed off-list, using 0x1fb_2000 would include regs that Kaanapali for example
> doesn't. So will use the 0x1fc_0000.
Urgh, I meant 0x1fb_f000.
Sorry about that.
On Tue, Jan 27, 2026 at 05:03:24PM +0200, Abel Vesa wrote: > Add the TCSR clock controller that provides the refclks on Eliza > platform for PCIe, USB and UFS subsystems. > > Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com> > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> > --- > drivers/clk/qcom/Kconfig | 8 +++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/tcsrcc-eliza.c | 144 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 153 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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