arch/x86/include/asm/kfence.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
The original patch inverted the PTE unconditionally to avoid
L1TF-vulnerable PTEs, but Linux doesn't make this adjustment in 2-level
paging.
Adjust the logic to use the flip_protnone_guard() helper, which is a nop on
2-level paging but inverts the address bits in all other paging modes.
This doesn't matter for the Xen aspect of the original change. Linux no
longer supports running 32bit PV under Xen, and Xen doesn't support running
any 32bit PV guests without using PAE paging.
Fixes: b505f1944535 ("x86/kfence: avoid writing L1TF-vulnerable PTEs")
Reported-by: Ryusuke Konishi <konishi.ryusuke@gmail.com>
Closes: https://lore.kernel.org/lkml/CAKFNMokwjw68ubYQM9WkzOuH51wLznHpEOMSqtMoV1Rn9JV_gw@mail.gmail.com/
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Ryusuke Konishi <konishi.ryusuke@gmail.com>
CC: Alexander Potapenko <glider@google.com>
CC: Marco Elver <elver@google.com>
CC: Dmitry Vyukov <dvyukov@google.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Ingo Molnar <mingo@redhat.com>
CC: Borislav Petkov <bp@alien8.de>
CC: Dave Hansen <dave.hansen@linux.intel.com>
CC: x86@kernel.org
CC: "H. Peter Anvin" <hpa@zytor.com>
CC: Andrew Morton <akpm@linux-foundation.org>
CC: Jann Horn <jannh@google.com>
CC: kasan-dev@googlegroups.com
CC: linux-kernel@vger.kernel.org
---
v2:
* Fix a spelling mistake in the comment.
---
arch/x86/include/asm/kfence.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/kfence.h b/arch/x86/include/asm/kfence.h
index acf9ffa1a171..dfd5c74ba41a 100644
--- a/arch/x86/include/asm/kfence.h
+++ b/arch/x86/include/asm/kfence.h
@@ -42,7 +42,7 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect)
{
unsigned int level;
pte_t *pte = lookup_address(addr, &level);
- pteval_t val;
+ pteval_t val, new;
if (WARN_ON(!pte || level != PG_LEVEL_4K))
return false;
@@ -57,11 +57,12 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect)
return true;
/*
- * Otherwise, invert the entire PTE. This avoids writing out an
+ * Otherwise, flip the Present bit, taking care to avoid writing an
* L1TF-vulnerable PTE (not present, without the high address bits
* set).
*/
- set_pte(pte, __pte(~val));
+ new = val ^ _PAGE_PRESENT;
+ set_pte(pte, __pte(flip_protnone_guard(val, new, PTE_PFN_MASK)));
/*
* If the page was protected (non-present) and we're making it
base-commit: fcb70a56f4d81450114034b2c61f48ce7444a0e2
--
2.39.5On Mon, 26 Jan 2026 21:10:46 +0000 Andrew Cooper <andrew.cooper3@citrix.com> wrote: > The original patch inverted the PTE unconditionally to avoid > L1TF-vulnerable PTEs, but Linux doesn't make this adjustment in 2-level > paging. > > Adjust the logic to use the flip_protnone_guard() helper, which is a nop on > 2-level paging but inverts the address bits in all other paging modes. > > This doesn't matter for the Xen aspect of the original change. Linux no > longer supports running 32bit PV under Xen, and Xen doesn't support running > any 32bit PV guests without using PAE paging. Great thanks. I'll add Tested-by: Ryusuke Konishi <konishi.ryusuke@gmail.com> and, importantly, Cc: <stable@vger.kernel.org> to help everything get threaded together correctly. I'll queue this as a 6.19-rcX hotfix.
On Mon, Jan 26, 2026 at 01:24:50PM -0800, Andrew Morton wrote:
> Great thanks. I'll add
>
> Tested-by: Ryusuke Konishi <konishi.ryusuke@gmail.com>
>
> and, importantly,
>
> Cc: <stable@vger.kernel.org>
>
> to help everything get threaded together correctly.
>
>
> I'll queue this as a 6.19-rcX hotfix.
You can add also
Tested-by: Borislav Petkov (AMD) <bp@alien8.de>
Works on a real hw too.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On 26/01/2026 9:56 pm, Borislav Petkov wrote: > On Mon, Jan 26, 2026 at 01:24:50PM -0800, Andrew Morton wrote: >> Great thanks. I'll add >> >> Tested-by: Ryusuke Konishi <konishi.ryusuke@gmail.com> >> >> and, importantly, >> >> Cc: <stable@vger.kernel.org> >> >> to help everything get threaded together correctly. >> >> >> I'll queue this as a 6.19-rcX hotfix. > You can add also > > Tested-by: Borislav Petkov (AMD) <bp@alien8.de> > > Works on a real hw too. Thanks, and sorry for the breakage. ~Andrew
On Mon, Jan 26, 2026 at 10:01:56PM +0000, Andrew Cooper wrote:
> Thanks, and sorry for the breakage.
Bah, no one cares about 32-bit. :-P
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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