s32g SoC family includes 2 serdes subsystems which are made of one PCIe
controller, 2 XPCS and a shared Phy. The Phy got 2 lanes that can be
configured to output PCIe lanes and/or SGMII.
Implement PCIe phy and XPCS support.
Vincent Guittot (4):
dt-bindings: serdes: s32g: Add NXP serdes subsystem
phy: s32g: Add serdes subsystem phy
phy: s32g: Add serdes xpcs subsystem
MAINTAINERS: Add MAINTAINER for NXP S32G Serdes driver
.../bindings/phy/nxp,s32g-serdes.yaml | 154 +++
MAINTAINERS | 9 +
drivers/phy/freescale/Kconfig | 10 +
drivers/phy/freescale/Makefile | 1 +
drivers/phy/freescale/phy-nxp-s32g-serdes.c | 926 ++++++++++++++
drivers/phy/freescale/phy-nxp-s32g-xpcs.c | 1082 +++++++++++++++++
drivers/phy/freescale/phy-nxp-s32g-xpcs.h | 47 +
include/linux/pcs/pcs-nxp-xpcs.h | 13 +
8 files changed, 2242 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
create mode 100644 drivers/phy/freescale/phy-nxp-s32g-serdes.c
create mode 100644 drivers/phy/freescale/phy-nxp-s32g-xpcs.c
create mode 100644 drivers/phy/freescale/phy-nxp-s32g-xpcs.h
create mode 100644 include/linux/pcs/pcs-nxp-xpcs.h
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2.43.0