[PATCH v2] bus: imx-aipstz: set default value for opacr registers

Shengjiu Wang posted 1 patch 1 week, 4 days ago
drivers/bus/imx-aipstz.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
[PATCH v2] bus: imx-aipstz: set default value for opacr registers
Posted by Shengjiu Wang 1 week, 4 days ago
The sdma script app_2_mcu needs the permission to access the peripheral
devices:

1) SDMA2 transactions are set to user-mode in this particular case.
2) This type of script doesn't use the peripheral interface (connected
directly to SPBA), but it uses the peripheral DMA interface, then the
SDMA2-issued transactions are subjected to AIPSTZ5's security-related
checks.

So need to clear the Supervisor Protect bit of SPBA2, otherwise the sdma
script can't work. As the imx-aipstz is a common driver for all aips bus,
so set default value (zero) for all opacr registers.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
Changes in v2:
- refine the commit message
- remove the unneeded initialize value

 drivers/bus/imx-aipstz.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/bus/imx-aipstz.c b/drivers/bus/imx-aipstz.c
index 5fdf377f5d06..83371e5b35a2 100644
--- a/drivers/bus/imx-aipstz.c
+++ b/drivers/bus/imx-aipstz.c
@@ -11,9 +11,19 @@
 #include <linux/regmap.h>
 
 #define IMX_AIPSTZ_MPR0 0x0
+#define IMX_AIPSTZ_OPACR0 0x40
+#define IMX_AIPSTZ_OPACR1 0x44
+#define IMX_AIPSTZ_OPACR2 0x48
+#define IMX_AIPSTZ_OPACR3 0x4c
+#define IMX_AIPSTZ_OPACR4 0x50
 
 struct imx_aipstz_config {
 	u32 mpr0;
+	u32 opacr0;
+	u32 opacr1;
+	u32 opacr2;
+	u32 opacr3;
+	u32 opacr4;
 };
 
 struct imx_aipstz_data {
@@ -24,6 +34,11 @@ struct imx_aipstz_data {
 static void imx_aipstz_apply_default(struct imx_aipstz_data *data)
 {
 	writel(data->default_cfg->mpr0, data->base + IMX_AIPSTZ_MPR0);
+	writel(data->default_cfg->opacr0, data->base + IMX_AIPSTZ_OPACR0);
+	writel(data->default_cfg->opacr1, data->base + IMX_AIPSTZ_OPACR1);
+	writel(data->default_cfg->opacr2, data->base + IMX_AIPSTZ_OPACR2);
+	writel(data->default_cfg->opacr3, data->base + IMX_AIPSTZ_OPACR3);
+	writel(data->default_cfg->opacr4, data->base + IMX_AIPSTZ_OPACR4);
 }
 
 static const struct of_device_id imx_aipstz_match_table[] = {
-- 
2.34.1
Re: [PATCH v2] bus: imx-aipstz: set default value for opacr registers
Posted by Frank Li 1 week, 4 days ago
On Mon, Jan 26, 2026 at 05:11:56PM +0800, Shengjiu Wang wrote:
> The sdma script app_2_mcu needs the permission to access the peripheral
> devices:
>
> 1) SDMA2 transactions are set to user-mode in this particular case.
> 2) This type of script doesn't use the peripheral interface (connected
> directly to SPBA), but it uses the peripheral DMA interface, then the
> SDMA2-issued transactions are subjected to AIPSTZ5's security-related
> checks.
>
> So need to clear the Supervisor Protect bit of SPBA2, otherwise the sdma
> script can't work. As the imx-aipstz is a common driver for all aips bus,
> so set default value (zero) for all opacr registers.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - refine the commit message
> - remove the unneeded initialize value
>
>  drivers/bus/imx-aipstz.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/bus/imx-aipstz.c b/drivers/bus/imx-aipstz.c
> index 5fdf377f5d06..83371e5b35a2 100644
> --- a/drivers/bus/imx-aipstz.c
> +++ b/drivers/bus/imx-aipstz.c
> @@ -11,9 +11,19 @@
>  #include <linux/regmap.h>
>
>  #define IMX_AIPSTZ_MPR0 0x0
> +#define IMX_AIPSTZ_OPACR0 0x40
> +#define IMX_AIPSTZ_OPACR1 0x44
> +#define IMX_AIPSTZ_OPACR2 0x48
> +#define IMX_AIPSTZ_OPACR3 0x4c
> +#define IMX_AIPSTZ_OPACR4 0x50
>
>  struct imx_aipstz_config {
>  	u32 mpr0;
> +	u32 opacr0;
> +	u32 opacr1;
> +	u32 opacr2;
> +	u32 opacr3;
> +	u32 opacr4;
>  };
>
>  struct imx_aipstz_data {
> @@ -24,6 +34,11 @@ struct imx_aipstz_data {
>  static void imx_aipstz_apply_default(struct imx_aipstz_data *data)
>  {
>  	writel(data->default_cfg->mpr0, data->base + IMX_AIPSTZ_MPR0);
> +	writel(data->default_cfg->opacr0, data->base + IMX_AIPSTZ_OPACR0);
> +	writel(data->default_cfg->opacr1, data->base + IMX_AIPSTZ_OPACR1);
> +	writel(data->default_cfg->opacr2, data->base + IMX_AIPSTZ_OPACR2);
> +	writel(data->default_cfg->opacr3, data->base + IMX_AIPSTZ_OPACR3);
> +	writel(data->default_cfg->opacr4, data->base + IMX_AIPSTZ_OPACR4);
>  }
>
>  static const struct of_device_id imx_aipstz_match_table[] = {
> --
> 2.34.1
>
Re: [PATCH v2] bus: imx-aipstz: set default value for opacr registers
Posted by Laurentiu Mihalcea 1 week, 4 days ago
On 1/26/2026 1:11 AM, Shengjiu Wang wrote:
> The sdma script app_2_mcu needs the permission to access the peripheral
> devices:
>
> 1) SDMA2 transactions are set to user-mode in this particular case.
> 2) This type of script doesn't use the peripheral interface (connected
> directly to SPBA), but it uses the peripheral DMA interface, then the
> SDMA2-issued transactions are subjected to AIPSTZ5's security-related
> checks.
>
> So need to clear the Supervisor Protect bit of SPBA2, otherwise the sdma
> script can't work. As the imx-aipstz is a common driver for all aips bus,
> so set default value (zero) for all opacr registers.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>


Reviewed-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Re: [PATCH v2] bus: imx-aipstz: set default value for opacr registers
Posted by Daniel Baluta 1 week, 4 days ago
On 1/26/26 11:11, Shengjiu Wang wrote:
> The sdma script app_2_mcu needs the permission to access the peripheral
> devices:
>
> 1) SDMA2 transactions are set to user-mode in this particular case.
> 2) This type of script doesn't use the peripheral interface (connected
> directly to SPBA), but it uses the peripheral DMA interface, then the
> SDMA2-issued transactions are subjected to AIPSTZ5's security-related
> checks.
>
> So need to clear the Supervisor Protect bit of SPBA2, otherwise the sdma
> script can't work. As the imx-aipstz is a common driver for all aips bus,
> so set default value (zero) for all opacr registers.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>