[PATCH V4 04/22] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP

Manikanta Maddireddy posted 22 patches 2 weeks ago
[PATCH V4 04/22] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP
Posted by Manikanta Maddireddy 2 weeks ago
From: Vidya Sagar <vidyas@nvidia.com>

PERST# and CLKREQ# pinctrl settings should be applied for both root port
and endpoint mode. Move pinctrl_pm_select_default_state() function call
from root port specific configuration function to probe().

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
V4:
* None

V3:
* None

V2:
* None

 drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 0b8c1a7ca232..04ff211deaea 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1645,12 +1645,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
 		goto fail_pm_get_sync;
 	}
 
-	ret = pinctrl_pm_select_default_state(dev);
-	if (ret < 0) {
-		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
-		goto fail_pm_get_sync;
-	}
-
 	ret = tegra_pcie_init_controller(pcie);
 	if (ret < 0) {
 		dev_err(dev, "Failed to initialize controller: %d\n", ret);
@@ -2106,6 +2100,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
 	pp = &pci->pp;
 	pp->num_vectors = MAX_MSI_IRQS;
 
+	ret = pinctrl_pm_select_default_state(dev);
+	if (ret < 0) {
+		const char *level = KERN_ERR;
+
+		if (ret == -EPROBE_DEFER)
+			level = KERN_DEBUG;
+
+		dev_printk(level, dev,
+			   "Failed to configure sideband pins: %d\n",
+			   ret);
+		return ret;
+	}
+
 	ret = tegra_pcie_dw_parse_dt(pcie);
 	if (ret < 0) {
 		const char *level = KERN_ERR;
-- 
2.34.1
Re: [PATCH V4 04/22] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP
Posted by Jon Hunter 1 week, 2 days ago

On 26/01/2026 07:45, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> PERST# and CLKREQ# pinctrl settings should be applied for both root port
> and endpoint mode. Move pinctrl_pm_select_default_state() function call
> from root port specific configuration function to probe().
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V4:
> * None
> 
> V3:
> * None
> 
> V2:
> * None
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------
>   1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 0b8c1a7ca232..04ff211deaea 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1645,12 +1645,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>   		goto fail_pm_get_sync;
>   	}
>   
> -	ret = pinctrl_pm_select_default_state(dev);
> -	if (ret < 0) {
> -		dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
> -		goto fail_pm_get_sync;
> -	}
> -
>   	ret = tegra_pcie_init_controller(pcie);
>   	if (ret < 0) {
>   		dev_err(dev, "Failed to initialize controller: %d\n", ret);
> @@ -2106,6 +2100,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>   	pp = &pci->pp;
>   	pp->num_vectors = MAX_MSI_IRQS;
>   
> +	ret = pinctrl_pm_select_default_state(dev);
> +	if (ret < 0) {
> +		const char *level = KERN_ERR;
> +
> +		if (ret == -EPROBE_DEFER)
> +			level = KERN_DEBUG;
> +
> +		dev_printk(level, dev,
> +			   "Failed to configure sideband pins: %d\n",
> +			   ret);

We can now use dev_err_probe() to handle the above and this becomes ...

  if (ret < 0)
         return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret);

> +		return ret;
> +	}
> +
>   	ret = tegra_pcie_dw_parse_dt(pcie);
>   	if (ret < 0) {
>   		const char *level = KERN_ERR;

-- 
nvpublic
Re: [PATCH V4 04/22] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP
Posted by Manikanta Maddireddy 1 week ago
On 30/01/26 10:51 pm, Jon Hunter wrote:
>
>
> On 26/01/2026 07:45, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> PERST# and CLKREQ# pinctrl settings should be applied for both root port
>> and endpoint mode. Move pinctrl_pm_select_default_state() function call
>> from root port specific configuration function to probe().
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> V4:
>> * None
>>
>> V3:
>> * None
>>
>> V2:
>> * None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------
>>   1 file changed, 13 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c 
>> b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 0b8c1a7ca232..04ff211deaea 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1645,12 +1645,6 @@ static int tegra_pcie_config_rp(struct 
>> tegra_pcie_dw *pcie)
>>           goto fail_pm_get_sync;
>>       }
>>   -    ret = pinctrl_pm_select_default_state(dev);
>> -    if (ret < 0) {
>> -        dev_err(dev, "Failed to configure sideband pins: %d\n", ret);
>> -        goto fail_pm_get_sync;
>> -    }
>> -
>>       ret = tegra_pcie_init_controller(pcie);
>>       if (ret < 0) {
>>           dev_err(dev, "Failed to initialize controller: %d\n", ret);
>> @@ -2106,6 +2100,19 @@ static int tegra_pcie_dw_probe(struct 
>> platform_device *pdev)
>>       pp = &pci->pp;
>>       pp->num_vectors = MAX_MSI_IRQS;
>>   +    ret = pinctrl_pm_select_default_state(dev);
>> +    if (ret < 0) {
>> +        const char *level = KERN_ERR;
>> +
>> +        if (ret == -EPROBE_DEFER)
>> +            level = KERN_DEBUG;
>> +
>> +        dev_printk(level, dev,
>> +               "Failed to configure sideband pins: %d\n",
>> +               ret);
>
> We can now use dev_err_probe() to handle the above and this becomes ...
>
>  if (ret < 0)
>         return dev_err_probe(dev, ret, "Failed to configure sideband 
> pins: %d\n", ret);
>
Thank you for quick review. I will fix it in next version.

I will wait for few more days for others to review this series and then 
send new version.

>> +        return ret;
>> +    }
>> +
>>       ret = tegra_pcie_dw_parse_dt(pcie);
>>       if (ret < 0) {
>>           const char *level = KERN_ERR;
>