From: Konrad Dybcio <konradybcio@kernel.org>
Add the required nodes to enable Venus on sc8280xp.
[ bod: added interconnect tags ]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[ johan: use sm8350 videocc defines ]
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
[ bod: dropped video encoder/decoder declarations ]
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
[ db: dropped llcc icc, switched to sc8280xp compat, added more freqs ]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 89 ++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 41c57e7dc433..66a65ae50f00 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -10,7 +10,9 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -691,6 +693,11 @@ reserved-region@85b00000 {
no-map;
};
+ pil_video_mem: pil_video_region@86700000 {
+ reg = <0 0x86700000 0 0x500000>;
+ no-map;
+ };
+
pil_adsp_mem: adsp-region@86c00000 {
reg = <0 0x86c00000 0 0x2000000>;
no-map;
@@ -4181,6 +4188,88 @@ usb_1_dwc3_ss: endpoint {
};
};
+ venus: video-codec@aa00000 {
+ compatible = "qcom,sc8280xp-venus";
+ reg = <0 0x0aa00000 0 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+ power-domains = <&videocc MVS0C_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd SC8280XP_MX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+ reset-names = "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ operating-points-v2 = <&venus_opp_table>;
+ iommus = <&apps_smmu 0x2e00 0x400>;
+ memory-region = <&pil_video_mem>;
+
+ status = "disabled";
+
+ venus_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-1098000000 {
+ opp-hz = /bits/ 64 <1098000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-1332000000 {
+ opp-hz = /bits/ 64 <1332000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-1599000000 {
+ opp-hz = /bits/ 64 <1599000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-1680000000 {
+ opp-hz = /bits/ 64 <1680000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sc8280xp-videocc";
+ reg = <0 0x0abf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
cci0: cci@ac4a000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4a000 0 0x1000>;
--
2.47.3
On 1/25/2026 9:03 PM, Dmitry Baryshkov wrote:
> From: Konrad Dybcio <konradybcio@kernel.org>
>
> Add the required nodes to enable Venus on sc8280xp.
>
> [ bod: added interconnect tags ]
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> [ johan: use sm8350 videocc defines ]
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> [ bod: dropped video encoder/decoder declarations ]
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> [ db: dropped llcc icc, switched to sc8280xp compat, added more freqs ]
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 89 ++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 41c57e7dc433..66a65ae50f00 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -10,7 +10,9 @@
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
> +#include <dt-bindings/clock/qcom,sm8350-videocc.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sc8280xp.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -691,6 +693,11 @@ reserved-region@85b00000 {
> no-map;
> };
>
> + pil_video_mem: pil_video_region@86700000 {
> + reg = <0 0x86700000 0 0x500000>;
> + no-map;
> + };
> +
> pil_adsp_mem: adsp-region@86c00000 {
> reg = <0 0x86c00000 0 0x2000000>;
> no-map;
> @@ -4181,6 +4188,88 @@ usb_1_dwc3_ss: endpoint {
> };
> };
>
> + venus: video-codec@aa00000 {
Pls name this as iris instead of venus.
> + compatible = "qcom,sc8280xp-venus";
> + reg = <0 0x0aa00000 0 0x100000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + <&videocc VIDEO_CC_MVS0C_CLK>,
> + <&videocc VIDEO_CC_MVS0_CLK>;
> + clock-names = "iface",
> + "core",
> + "vcodec0_core";
> + power-domains = <&videocc MVS0C_GDSC>,
> + <&videocc MVS0_GDSC>,
> + <&rpmhpd SC8280XP_MX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "mx";
> +
> + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
> + reset-names = "core";
should be names as 'bus'
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "cpu-cfg",
> + "video-mem";
> +
> + operating-points-v2 = <&venus_opp_table>;
s/venus_opp_table/iris_opp_table
> + iommus = <&apps_smmu 0x2e00 0x400>;
> + memory-region = <&pil_video_mem>;
> +
> + status = "disabled";
> +
> + venus_opp_table: opp-table {
> + compatible = "operating-points-v2";
Thanks,
Dikshita
On 1/25/26 4:33 PM, Dmitry Baryshkov wrote:
> From: Konrad Dybcio <konradybcio@kernel.org>
>
> Add the required nodes to enable Venus on sc8280xp.
>
> [ bod: added interconnect tags ]
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> [ johan: use sm8350 videocc defines ]
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> [ bod: dropped video encoder/decoder declarations ]
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> [ db: dropped llcc icc, switched to sc8280xp compat, added more freqs ]
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
[...]
> + venus_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-720000000 {
> + opp-hz = /bits/ 64 <720000000>;
You need to div3 all of these, otherwise this LOW_SVS OPP
will actually apply a more-than-TURBO_L1-requiring frequency..
[...]
> + videocc: clock-controller@abf0000 {
> + compatible = "qcom,sc8280xp-videocc";
> + reg = <0 0x0abf0000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>;
> + power-domains = <&rpmhpd SC8280XP_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
AFAICS the PLLs will not turn on if *MX* is at < LOWSVS, but they still
need to be scaled 1:1 with MMCX as the freuqency rises, so you need to
wire up 2 power domains to the OPP table
PLL0 supplies core0 (iris) and PLL1 supplies core1 (CVP)
Konrad
On Mon, Jan 26, 2026 at 11:00:25AM +0100, Konrad Dybcio wrote:
> On 1/25/26 4:33 PM, Dmitry Baryshkov wrote:
> > From: Konrad Dybcio <konradybcio@kernel.org>
> >
> > Add the required nodes to enable Venus on sc8280xp.
> >
> > [ bod: added interconnect tags ]
> >
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > [ johan: use sm8350 videocc defines ]
> > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
> > [ bod: dropped video encoder/decoder declarations ]
> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> > [ db: dropped llcc icc, switched to sc8280xp compat, added more freqs ]
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + venus_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-720000000 {
> > + opp-hz = /bits/ 64 <720000000>;
>
> You need to div3 all of these, otherwise this LOW_SVS OPP
> will actually apply a more-than-TURBO_L1-requiring frequency..
Hmm, is the OPP table for SM8250 then also incorrect?
I cross-checked SM8250 and Kodiak against, msm-4.19 and msm-5.4
correspondignly, the OPP tables are written in the same way.
>
> [...]
> > + videocc: clock-controller@abf0000 {
> > + compatible = "qcom,sc8280xp-videocc";
> > + reg = <0 0x0abf0000 0 0x10000>;
> > + clocks = <&rpmhcc RPMH_CXO_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK_A>,
> > + <&sleep_clk>;
> > + power-domains = <&rpmhpd SC8280XP_MMCX>;
> > + required-opps = <&rpmhpd_opp_low_svs>;
>
> AFAICS the PLLs will not turn on if *MX* is at < LOWSVS, but they still
> need to be scaled 1:1 with MMCX as the freuqency rises, so you need to
> wire up 2 power domains to the OPP table
I don't see this being done for SM8250, should it also be fixed? On
SM8550 we indeed manage MMCX and MX together. Should SC7280 also scale
both CX and MX together?
>
> PLL0 supplies core0 (iris) and PLL1 supplies core1 (CVP)
--
On 1/26/26 11:47 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 26, 2026 at 11:00:25AM +0100, Konrad Dybcio wrote:
>> On 1/25/26 4:33 PM, Dmitry Baryshkov wrote:
>>> From: Konrad Dybcio <konradybcio@kernel.org>
>>>
>>> Add the required nodes to enable Venus on sc8280xp.
>>>
>>> [ bod: added interconnect tags ]
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> [ johan: use sm8350 videocc defines ]
>>> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
>>> [ bod: dropped video encoder/decoder declarations ]
>>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>>> [ db: dropped llcc icc, switched to sc8280xp compat, added more freqs ]
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + venus_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-720000000 {
>>> + opp-hz = /bits/ 64 <720000000>;
>>
>> You need to div3 all of these, otherwise this LOW_SVS OPP
>> will actually apply a more-than-TURBO_L1-requiring frequency..
>
> Hmm, is the OPP table for SM8250 then also incorrect?
The OPP-set clock is "vcodec0_core"
The DT references VIDEO_CC_MVS0_CLK, which is a branch-child of
video_cc_mvs0_div_clk_src, so that sounds like it makes sense..
And the frequency plan concurs that.
>
> I cross-checked SM8250 and Kodiak against, msm-4.19 and msm-5.4
> correspondignly, the OPP tables are written in the same way.
>
>>
>> [...]
>>> + videocc: clock-controller@abf0000 {
>>> + compatible = "qcom,sc8280xp-videocc";
>>> + reg = <0 0x0abf0000 0 0x10000>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> + <&rpmhcc RPMH_CXO_CLK_A>,
>>> + <&sleep_clk>;
>>> + power-domains = <&rpmhpd SC8280XP_MMCX>;
>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>
>> AFAICS the PLLs will not turn on if *MX* is at < LOWSVS, but they still
>> need to be scaled 1:1 with MMCX as the freuqency rises, so you need to
>> wire up 2 power domains to the OPP table
>
> I don't see this being done for SM8250, should it also be fixed? On
> SM8550 we indeed manage MMCX and MX together. Should SC7280 also scale
> both CX and MX together?
8250 yes
On kodiak, the docs strangely say that it's *all* powered by CX, maybe
+Taniya or +Jagadeesh could confirm if that's right
Konrad
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