Add compatible string for Glymur video clock controller and the bindings
for Glymur Qualcomm SoC. Add the clock resets required from the GCC
clock controller for Video.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++
include/dt-bindings/clock/qcom,glymur-gcc.h | 1 +
include/dt-bindings/clock/qcom,glymur-videocc.h | 45 ++++++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
index e6beebd6a36ee1ce213a816f60df8a76fa5c44d6..7bbf120d928cc506a4f7aaeaa1c24e5da760e450 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -15,6 +15,7 @@ description: |
domains on SM8450.
See also:
+ include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
@@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
@@ -63,6 +65,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h
index 10c12b8c51c34c5931c34b4437be03aea098ba53..6907653c79927f0ff32c98c75d830b719ce14d51 100644
--- a/include/dt-bindings/clock/qcom,glymur-gcc.h
+++ b/include/dt-bindings/clock/qcom,glymur-gcc.h
@@ -574,5 +574,6 @@
#define GCC_VIDEO_AXI0_CLK_ARES 89
#define GCC_VIDEO_AXI1_CLK_ARES 90
#define GCC_VIDEO_BCR 91
+#define GCC_VIDEO_AXI0C_CLK_ARES 92
#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-videocc.h b/include/dt-bindings/clock/qcom,glymur-videocc.h
new file mode 100644
index 0000000000000000000000000000000000000000..98c0debef8fa9d67a2fb86a0e42d6e207ad89c09
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-videocc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK 0
+#define VIDEO_CC_AHB_CLK_SRC 1
+#define VIDEO_CC_MVS0_CLK 2
+#define VIDEO_CC_MVS0_CLK_SRC 3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
+#define VIDEO_CC_MVS0_FREERUN_CLK 5
+#define VIDEO_CC_MVS0_SHIFT_CLK 6
+#define VIDEO_CC_MVS0C_CLK 7
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
+#define VIDEO_CC_MVS0C_FREERUN_CLK 9
+#define VIDEO_CC_MVS0C_SHIFT_CLK 10
+#define VIDEO_CC_MVS1_CLK 11
+#define VIDEO_CC_MVS1_DIV_CLK_SRC 12
+#define VIDEO_CC_MVS1_FREERUN_CLK 13
+#define VIDEO_CC_MVS1_SHIFT_CLK 14
+#define VIDEO_CC_PLL0 15
+#define VIDEO_CC_SLEEP_CLK 16
+#define VIDEO_CC_SLEEP_CLK_SRC 17
+#define VIDEO_CC_XO_CLK 18
+#define VIDEO_CC_XO_CLK_SRC 19
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC 0
+#define VIDEO_CC_MVS0C_GDSC 1
+#define VIDEO_CC_MVS1_GDSC 2
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR 0
+#define VIDEO_CC_MVS0_BCR 1
+#define VIDEO_CC_MVS0C_BCR 2
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 3
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4
+#define VIDEO_CC_MVS1_FREERUN_CLK_ARES 5
+#define VIDEO_CC_XO_CLK_ARES 6
+#define VIDEO_CC_MVS1_BCR 7
+#endif
--
2.34.1On Sat, Jan 24, 2026 at 11:05:02PM +0530, Taniya Das wrote: > Add compatible string for Glymur video clock controller and the bindings > for Glymur Qualcomm SoC. Add the clock resets required from the GCC > clock controller for Video. > > Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> > --- > .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++ > include/dt-bindings/clock/qcom,glymur-gcc.h | 1 + > include/dt-bindings/clock/qcom,glymur-videocc.h | 45 ++++++++++++++++++++++ > 3 files changed, 49 insertions(+) > > diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h > index 10c12b8c51c34c5931c34b4437be03aea098ba53..6907653c79927f0ff32c98c75d830b719ce14d51 100644 > --- a/include/dt-bindings/clock/qcom,glymur-gcc.h > +++ b/include/dt-bindings/clock/qcom,glymur-gcc.h > @@ -574,5 +574,6 @@ > #define GCC_VIDEO_AXI0_CLK_ARES 89 > #define GCC_VIDEO_AXI1_CLK_ARES 90 > #define GCC_VIDEO_BCR 91 > +#define GCC_VIDEO_AXI0C_CLK_ARES 92 I think this one should be split to a separate patch and paired with the corresponding driver change. > > #endif -- With best wishes Dmitry
On 1/25/2026 1:50 AM, Dmitry Baryshkov wrote: > On Sat, Jan 24, 2026 at 11:05:02PM +0530, Taniya Das wrote: >> Add compatible string for Glymur video clock controller and the bindings >> for Glymur Qualcomm SoC. Add the clock resets required from the GCC >> clock controller for Video. >> >> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> >> --- >> .../bindings/clock/qcom,sm8450-videocc.yaml | 3 ++ >> include/dt-bindings/clock/qcom,glymur-gcc.h | 1 + >> include/dt-bindings/clock/qcom,glymur-videocc.h | 45 ++++++++++++++++++++++ >> 3 files changed, 49 insertions(+) >> >> diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h >> index 10c12b8c51c34c5931c34b4437be03aea098ba53..6907653c79927f0ff32c98c75d830b719ce14d51 100644 >> --- a/include/dt-bindings/clock/qcom,glymur-gcc.h >> +++ b/include/dt-bindings/clock/qcom,glymur-gcc.h >> @@ -574,5 +574,6 @@ >> #define GCC_VIDEO_AXI0_CLK_ARES 89 >> #define GCC_VIDEO_AXI1_CLK_ARES 90 >> #define GCC_VIDEO_BCR 91 >> +#define GCC_VIDEO_AXI0C_CLK_ARES 92 > > I think this one should be split to a separate patch and paired with the > corresponding driver change. > Sure, will split it up. >> >> #endif > -- Thanks, Taniya Das
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