The Aspeed 7th generation SoC features two SGPIO master controllers: both
with 256 serial inputs and outputs. The main difference from the previous
generation is that the control logic has been updated to support
per-pin control, allowing each pin to have its own 32-bit register for
configuring value, interrupt type, and more.
This patch serial also add low-level operations (llops) to abstract the
register access for SGPIO registers making it easier to extend the driver
to support different hardware register layouts.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
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Changes in v2:
- Split the IRQ-related llops conversion into a separate patch to keep changes logically scoped.
- Minimized unrelated changes (such as variable renaming) to reduce diff noise and ease review.
- Clarified the llops design intent and semantics.
- Link to v1: https://lore.kernel.org/r/20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com
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Billy Tsai (6):
gpio: aspeed-sgpio: Change the macro to support deferred probe
gpio: aspeed-sgpio: Remove unused bank name field
gpio: aspeed-sgpio: Create llops to handle hardware access
gpio: aspeed-sgpio: Convert IRQ functions to use llops callbacks
dt-bindings: gpio: aspeed,sgpio: Support ast2700
gpio: aspeed-sgpio: Support G7 Aspeed sgpiom controller
.../devicetree/bindings/gpio/aspeed,sgpio.yaml | 4 +-
drivers/gpio/gpio-aspeed-sgpio.c | 362 +++++++++++++--------
2 files changed, 227 insertions(+), 139 deletions(-)
---
base-commit: 39d3389331abd712461f50249722f7ed9d815068
change-id: 20251223-upstream_sgpio-70d815c64a19
Best regards,
--
Billy Tsai <billy_tsai@aspeedtech.com>