Document the stm32 debug bus. The debug bus is responsible for
checking the debug sub-system accessibility before probing any related
drivers.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
.../bindings/bus/st,stm32mp131-dbg-bus.yaml | 76 ++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
new file mode 100644
index 000000000000..6c74433efbe3
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Coresight bus
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+description:
+ The STM32 debug bus is in charge of checking the debug configuration
+ of the platform before probing the peripheral drivers that rely on the debug
+ domain.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - st,stm32mp131-dbg-bus
+ - st,stm32mp151-dbg-bus
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges:
+ minItems: 1
+ maxItems: 2
+
+ "#access-controller-cells":
+ const: 1
+ description:
+ Contains the debug profile necessary to access the peripheral.
+
+patternProperties:
+ "@[0-9a-f]+$":
+ description: Debug related peripherals
+ type: object
+
+ additionalProperties: true
+
+ required:
+ - access-controllers
+
+required:
+ - "#access-controller-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+
+ dbg_bus: bus@50080000 {
+ compatible = "st,stm32mp131-dbg-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges = <0x50080000 0x50080000 0x3f80000>;
+
+ cti@50094000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ };
+ };
--
2.43.0
On Fri, 23 Jan 2026 11:39:00 +0100, Gatien Chevallier wrote: > Document the stm32 debug bus. The debug bus is responsible for > checking the debug sub-system accessibility before probing any related > drivers. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > --- > .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 76 ++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Hello,
Does this binding file satisfy the feedback received?
Thanks,
Gatien
On 1/23/26 11:39, Gatien Chevallier wrote:
> Document the stm32 debug bus. The debug bus is responsible for
> checking the debug sub-system accessibility before probing any related
> drivers.
>
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 76 ++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
> new file mode 100644
> index 000000000000..6c74433efbe3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STM32 Coresight bus
> +
> +maintainers:
> + - Gatien Chevallier <gatien.chevallier@foss.st.com>
> +
> +description:
> + The STM32 debug bus is in charge of checking the debug configuration
> + of the platform before probing the peripheral drivers that rely on the debug
> + domain.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - st,stm32mp131-dbg-bus
> + - st,stm32mp151-dbg-bus
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges:
> + minItems: 1
> + maxItems: 2
> +
> + "#access-controller-cells":
> + const: 1
> + description:
> + Contains the debug profile necessary to access the peripheral.
> +
> +patternProperties:
> + "@[0-9a-f]+$":
> + description: Debug related peripherals
> + type: object
> +
> + additionalProperties: true
> +
> + required:
> + - access-controllers
> +
> +required:
> + - "#access-controller-cells"
> + - "#address-cells"
> + - "#size-cells"
> + - compatible
> + - ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/stm32mp1-clks.h>
> +
> + dbg_bus: bus@50080000 {
> + compatible = "st,stm32mp131-dbg-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #access-controller-cells = <1>;
> + ranges = <0x50080000 0x50080000 0x3f80000>;
> +
> + cti@50094000 {
> + compatible = "arm,coresight-cti", "arm,primecell";
> + reg = <0x50094000 0x1000>;
> + clocks = <&rcc CK_DBG>;
> + clock-names = "apb_pclk";
> + access-controllers = <&dbg_bus 0>;
> + };
> + };
>
On Wed, Jan 28, 2026 at 03:23:45PM +0100, Gatien CHEVALLIER wrote:
> Hello,
>
> Does this binding file satisfy the feedback received?
Please check patchwork if you want to know the status of your patch.
>
> Thanks,
> Gatien
>
> On 1/23/26 11:39, Gatien Chevallier wrote:
> > Document the stm32 debug bus. The debug bus is responsible for
> > checking the debug sub-system accessibility before probing any related
> > drivers.
> >
> > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> > ---
> > .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 76 ++++++++++++++++++++++
> > 1 file changed, 76 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
> > new file mode 100644
> > index 000000000000..6c74433efbe3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: STM32 Coresight bus
> > +
> > +maintainers:
> > + - Gatien Chevallier <gatien.chevallier@foss.st.com>
> > +
> > +description:
> > + The STM32 debug bus is in charge of checking the debug configuration
> > + of the platform before probing the peripheral drivers that rely on the debug
> > + domain.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - st,stm32mp131-dbg-bus
> > + - st,stm32mp151-dbg-bus
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > + ranges:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + "#access-controller-cells":
> > + const: 1
> > + description:
> > + Contains the debug profile necessary to access the peripheral.
> > +
> > +patternProperties:
> > + "@[0-9a-f]+$":
> > + description: Debug related peripherals
> > + type: object
> > +
> > + additionalProperties: true
> > +
> > + required:
> > + - access-controllers
> > +
> > +required:
> > + - "#access-controller-cells"
> > + - "#address-cells"
> > + - "#size-cells"
> > + - compatible
> > + - ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/stm32mp1-clks.h>
> > +
> > + dbg_bus: bus@50080000 {
> > + compatible = "st,stm32mp131-dbg-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + #access-controller-cells = <1>;
> > + ranges = <0x50080000 0x50080000 0x3f80000>;
> > +
> > + cti@50094000 {
> > + compatible = "arm,coresight-cti", "arm,primecell";
> > + reg = <0x50094000 0x1000>;
> > + clocks = <&rcc CK_DBG>;
> > + clock-names = "apb_pclk";
> > + access-controllers = <&dbg_bus 0>;
> > + };
> > + };
> >
>
© 2016 - 2026 Red Hat, Inc.