Replace do_div() with div64_ul() since the remainder is not used.
div64_ul() is the preferred API for 64-bit by 32-bit division when
only the quotient is needed, as it returns the result directly rather
than modifying the dividend in-place.

Issue identified by coccicheck using do_div.cocci.

Signed-off-by: Archit Anant <architanant5@gmail.com>
---
 drivers/staging/iio/impedance-analyzer/ad5933.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/iio/impedance-analyzer/ad5933.c b/drivers/staging/iio/impedance-analyzer/ad5933.c
index 85a4223295cd..772267f6f093 100644
--- a/drivers/staging/iio/impedance-analyzer/ad5933.c
+++ b/drivers/staging/iio/impedance-analyzer/ad5933.c
@@ -194,8 +194,8 @@ static int ad5933_set_freq(struct ad5933_state *st,
 		u8 d8[4];
 	} dat;
 
-	freqreg = (u64)freq * (u64)(1 << 27);
-	do_div(freqreg, st->mclk_hz / 4);
+	freqreg = div64_ul((u64)freq * (u64)(1 << 27),
+			   st->mclk_hz / 4);
 
 	switch (reg) {
 	case AD5933_REG_FREQ_START:
-- 
2.39.5

On Thu, Jan 22, 2026 at 08:26:33PM +0530, Archit Anant wrote:
> Replace do_div() with div64_ul() since the remainder is not used.
> div64_ul() is the preferred API for 64-bit by 32-bit division when
> only the quotient is needed, as it returns the result directly rather
> than modifying the dividend in-place.
> 
> Issue identified by coccicheck using do_div.cocci.

...

> -	freqreg = (u64)freq * (u64)(1 << 27);
> -	do_div(freqreg, st->mclk_hz / 4);
> +	freqreg = div64_ul((u64)freq * (u64)(1 << 27),
> +			   st->mclk_hz / 4);

It can be one line to begin with.
Then drop that ugly castings and explicit big shifts.

	freqreg = div64_ul(BIT_ULL(27) * freq, st->mclk_hz / 4);

Now you can see That 4 is only 2 bits, so this can be written in
simpler way:

	freqreg = div64_ul(BIT_ULL(29) * freq, st->mclk_hz);

which may give a better precision at the end of the day.

-- 
With Best Regards,
Andy Shevchenko

On Thu, Jan 22, 2026 at 05:12:42PM +0200, Andy Shevchenko wrote:
> On Thu, Jan 22, 2026 at 08:26:33PM +0530, Archit Anant wrote:

...

> > -	freqreg = (u64)freq * (u64)(1 << 27);
> > -	do_div(freqreg, st->mclk_hz / 4);
> > +	freqreg = div64_ul((u64)freq * (u64)(1 << 27),
> > +			   st->mclk_hz / 4);
> 
> It can be one line to begin with.
> Then drop that ugly castings and explicit big shifts.
> 
> 	freqreg = div64_ul(BIT_ULL(27) * freq, st->mclk_hz / 4);
> 
> Now you can see That 4 is only 2 bits, so this can be written in
> simpler way:
> 
> 	freqreg = div64_ul(BIT_ULL(29) * freq, st->mclk_hz);
> 
> which may give a better precision at the end of the day.

It also might be worth to add a comment on top to explain (with given context
I don't know if there is already one on top of the function, though).

And I think we want AD people to comment on this and maybe explain better
the calculations done (and why the original code drops precision, was it
deliberate?).

-- 
With Best Regards,
Andy Shevchenko