UFS controller v6.2 requires bit 31 in the spare configuration register
to be set for high-speed link startup mode, as per the Hardware
Programming Guide (HPG).

The spare register value is read during host driver initialization but
gets cleared after UFS reset. To align with the UFS v6.2 programming
sequence, preserve the spare register value during initialization and
restore it during link startup to ensure proper high-speed mode

Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
---
 drivers/ufs/host/ufs-qcom.c | 11 ++++++++---
 drivers/ufs/host/ufs-qcom.h |  1 +
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index c43bb75d208c..ab5aed241913 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 					enum ufs_notify_change_status status)
 {
+	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 	int err = 0;

 	switch (status) {
@@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 		 */
 		err = ufshcd_disable_host_tx_lcc(hba);

+		/* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */
+		if (host->hw_ver.major == 0x6 && host->hw_ver.minor == 0x2)
+			ufshcd_writel(hba, host->spare_cfg,
+				      REG_UFS_DEBUG_SPARE_CFG);
 		break;
 	default:
 		break;
@@ -1084,7 +1089,7 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
 {
 	struct ufs_host_params *host_params = &host->host_params;
-	u32 val, dev_major;
+	u32 dev_major;

 	/*
 	 * Default to powering up the PHY to the max gear possible, which is
@@ -1103,8 +1108,8 @@ static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
 		 */
 		host->phy_gear = UFS_HS_G2;
 	} else if (host->hw_ver.major >= 0x5) {
-		val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
-		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
+		host->spare_cfg = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
+		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, host->spare_cfg);

 		/*
 		 * Since the UFS device version is populated, let's remove the
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 380d02333d38..d09ef7f44305 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -308,6 +308,7 @@ struct ufs_qcom_host {
 	u32 phy_gear;

 	bool esi_enabled;
+	u32 spare_cfg;
 };

 struct ufs_qcom_drvdata {
--
2.34.1

On 1/22/26 3:13 PM, Nitin Rawat wrote:
> UFS controller v6.2 requires bit 31 in the spare configuration register
> to be set for high-speed link startup mode, as per the Hardware
> Programming Guide (HPG).

Please stick a "Qualcomm" before mentioning UFS controller v6.2, I
don't think that is immediately obvious without looking at the code..

> The spare register value is read during host driver initialization but
> gets cleared after UFS reset. To align with the UFS v6.2 programming
> sequence, preserve the spare register value during initialization and
> restore it during link startup to ensure proper high-speed mode

I believe you're supposed to write the value yourself, depending on the
state of the controller, it's 0 at reset.

> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> ---
>  drivers/ufs/host/ufs-qcom.c | 11 ++++++++---
>  drivers/ufs/host/ufs-qcom.h |  1 +
>  2 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index c43bb75d208c..ab5aed241913 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
>  static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>  					enum ufs_notify_change_status status)
>  {
> +	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>  	int err = 0;
> 
>  	switch (status) {
> @@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>  		 */
>  		err = ufshcd_disable_host_tx_lcc(hba);
> 
> +		/* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */

"HS/LS"?

> +		if (host->hw_ver.major == 0x6 && host->hw_ver.minor == 0x2)
> +			ufshcd_writel(hba, host->spare_cfg,
> +				      REG_UFS_DEBUG_SPARE_CFG);

Is that a "only on v6.2", or "starting with v6.2"?

Also, I see that this register has more than just this one field, with
the previous question in mind, I think a rmw would be desired here

Konrad