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[PATCH] clk: vf610: Add support for the Ethernet switch clocks

Lukasz Majewski posted 1 patch 2 weeks, 2 days ago
There is a newer version of this series
drivers/clk/imx/clk-vf610.c | 5 +++++
1 file changed, 5 insertions(+)
[PATCH] clk: vf610: Add support for the Ethernet switch clocks
Posted by Lukasz Majewski 2 weeks, 2 days ago 
The vf610 device has built in the MoreThanIP L2 switch. For proper
operation it is required to enable ESW and MAC table lookup
clocks.

The MAC table spans from 0x400E_C000 for 0x4000 and it is necessary
to provide clocks for each AIPS1-"slot", which size is 0x1000
(hence four separate entries).

Those can be enabled via clock gating CCM_CCGR10 register
(0x4006_B068).

Signed-off-by: Lukasz Majewski <lukma@nabladev.com>
---
 drivers/clk/imx/clk-vf610.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 9e11f1c7c397..88c9b656f244 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -309,6 +309,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
 	clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
 	clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
 	clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
+	clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
+	clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));
+	clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));
+	clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));
+	clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));
 
 	clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
 
-- 
2.39.5
Re: [PATCH] clk: vf610: Add support for the Ethernet switch clocks
Posted by Andrew Lunn 2 weeks, 1 day ago 
On Thu, Jan 22, 2026 at 02:06:49PM +0100, Lukasz Majewski wrote:
> The vf610 device has built in the MoreThanIP L2 switch. For proper
> operation it is required to enable ESW and MAC table lookup
> clocks.
> 
> The MAC table spans from 0x400E_C000 for 0x4000 and it is necessary
> to provide clocks for each AIPS1-"slot", which size is 0x1000
> (hence four separate entries).
> 
> Those can be enabled via clock gating CCM_CCGR10 register
> (0x4006_B068).

Sorry, i lost track of the state of the switch driver. Is there also a
patch to add consumers of these clocks?

> Signed-off-by: Lukasz Majewski <lukma@nabladev.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
Re: [PATCH] clk: vf610: Add support for the Ethernet switch clocks
Posted by Łukasz Majewski 2 weeks, 1 day ago 
Hi Andrew,

> On Thu, Jan 22, 2026 at 02:06:49PM +0100, Lukasz Majewski wrote:
> > The vf610 device has built in the MoreThanIP L2 switch. For proper
> > operation it is required to enable ESW and MAC table lookup
> > clocks.
> > 
> > The MAC table spans from 0x400E_C000 for 0x4000 and it is necessary
> > to provide clocks for each AIPS1-"slot", which size is 0x1000
> > (hence four separate entries).
> > 
> > Those can be enabled via clock gating CCM_CCGR10 register
> > (0x4006_B068).  
> 
> Sorry, i lost track of the state of the switch driver.

New year, new MTIP L2 switch patches in preparation :-)

> Is there also a
> patch to add consumers of these clocks?

In short - this patch set is a preparatory one for vf610 SoC support of
the MTIP L2 switch.

Those changes describe more thoroughly the clock subsystem of this SoC.

> 
> > Signed-off-by: Lukasz Majewski <lukma@nabladev.com>  
> 
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> 
>     Andrew

-- 
Best regards,

Lukasz Majewski

--
Nabla Software Engineering GmbH
HRB 40522 Augsburg
Phone: +49 821 45592596
E-Mail: office@nabladev.com
Managing Director : Stefano Babic
Re: [PATCH] clk: vf610: Add support for the Ethernet switch clocks
Posted by Łukasz Majewski 2 weeks, 1 day ago 
Hi Andrew,

> Hi Andrew,
> 
> > On Thu, Jan 22, 2026 at 02:06:49PM +0100, Lukasz Majewski wrote:  
> > > The vf610 device has built in the MoreThanIP L2 switch. For proper
> > > operation it is required to enable ESW and MAC table lookup
> > > clocks.
> > > 
> > > The MAC table spans from 0x400E_C000 for 0x4000 and it is
> > > necessary to provide clocks for each AIPS1-"slot", which size is
> > > 0x1000 (hence four separate entries).
> > > 
> > > Those can be enabled via clock gating CCM_CCGR10 register
> > > (0x4006_B068).    
> > 
> > Sorry, i lost track of the state of the switch driver.  
> 
> New year, new MTIP L2 switch patches in preparation :-)
> 

Just to share:
https://github.com/lmajewski/linux-imx28-l2switch/commits/vf610-linux-6.6.y-mtipl2sw

The driver has been tested (after backporting) on v6.6 LTS with
PREEMPT_RT.

Moreover, I've added support for switchdev.

> > Is there also a
> > patch to add consumers of these clocks?  
> 
> In short - this patch set is a preparatory one for vf610 SoC support
> of the MTIP L2 switch.
> 
> Those changes describe more thoroughly the clock subsystem of this
> SoC.
> 
> >   
> > > Signed-off-by: Lukasz Majewski <lukma@nabladev.com>    
> > 
> > Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> > 
> >     Andrew  
> 



-- 
Best regards,

Lukasz Majewski

--
Nabla Software Engineering GmbH
HRB 40522 Augsburg
Phone: +49 821 45592596
E-Mail: office@nabladev.com
Managing Director : Stefano Babic
Re: [PATCH] clk: vf610: Add support for the Ethernet switch clocks
Posted by Frank Li 2 weeks, 2 days ago 
On Thu, Jan 22, 2026 at 02:06:49PM +0100, Lukasz Majewski wrote:
> The vf610 device has built in the MoreThanIP L2 switch. For proper
> operation it is required to enable ESW and MAC table lookup
> clocks.
>
> The MAC table spans from 0x400E_C000 for 0x4000 and it is necessary
> to provide clocks for each AIPS1-"slot", which size is 0x1000
> (hence four separate entries).
>
> Those can be enabled via clock gating CCM_CCGR10 register
> (0x4006_B068).
>
> Signed-off-by: Lukasz Majewski <lukma@nabladev.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/clk/imx/clk-vf610.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
> index 9e11f1c7c397..88c9b656f244 100644
> --- a/drivers/clk/imx/clk-vf610.c
> +++ b/drivers/clk/imx/clk-vf610.c
> @@ -309,6 +309,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
>  	clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
>  	clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
>  	clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
> +	clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
> +	clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));
> +	clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));
> +	clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));
> +	clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));
>
>  	clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
>
> --
> 2.39.5
>

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