Add support for the Renesas RZ/N1D400 QSPI controller.
This SoC is identified in the bindings with its other name: r9a06g032.
It is part of the RZ/N1 family, which contains a "D" and a "S"
variant. IPs in this SoC are typically described using 2 compatibles:
the SoC specific compatible and the family compatible. The original
Cadence IP compatible is dropped because it is unusable on its own.
Indirect accesses are not supported by this flavour of the Cadence IP,
which means several properties have no meaning in the scope of the
Renesas compatible. Let's make sure they are no longer expected nor
mandatory.
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
.../devicetree/bindings/spi/cdns,qspi-nor.yaml | 33 ++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index e005869a76c8..43625f41131d 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -61,6 +61,20 @@ allOf:
cdns,fifo-depth:
enum: [ 128, 256 ]
default: 128
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzn1-qspi
+ then:
+ properties:
+ cdns,trigger-address: false
+ cdns,fifo-depth: false
+ cdns,fifo-width: false
+ else:
+ required:
+ - cdns,trigger-address
+ - cdns,fifo-depth
properties:
compatible:
@@ -80,6 +94,9 @@ properties:
# controllers are meant to be used with flashes of all kinds,
# ie. also NAND flashes, not only NOR flashes.
- const: cdns,qspi-nor
+ - items:
+ - const: renesas,r9a06g032-qspi
+ - const: renesas,rzn1-qspi
- const: cdns,qspi-nor
deprecated: true
@@ -163,8 +180,6 @@ required:
- reg
- interrupts
- clocks
- - cdns,fifo-width
- - cdns,trigger-address
- '#address-cells'
- '#size-cells'
@@ -231,3 +246,17 @@ examples:
cdns,fifo-width = <4>;
cdns,trigger-address = <0x7fff0000>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+ spi@40005000 {
+ compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi";
+ reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
+ <&sysctrl R9A06G032_HCLK_QSPI0>;
+ clock-names = "ref", "ahb", "apb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
--
2.51.1