.../devicetree/bindings/spi/cdns,qspi-nor.yaml | 35 ++- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 12 + drivers/spi/spi-cadence-quadspi.c | 279 ++++++++++----------- 3 files changed, 177 insertions(+), 149 deletions(-)
Hello,
This series adds support for the QSPI controller available on Renesas
RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
SPI patch for details), but has been tested by Wolfram (thank you!) on
the DB board.
Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/
Adding support for this SoC required a few adaptations in the Cadence
QSPI driver. The bulk of the work is in the few last patches. Everything
else is just misc style fixes and improvements which bothered me while I
was wandering.
In order to support all constraints, I sometimes used a new quirk (for
the write protection feature and the "no indirect mode"), and sometimes
used the compatible directly. The ones I thought might not be RZ/N1
specific have been implemented under the form of a quirk, in order to
ease their reuse. The other adaptations, which I believe are more
Renesas specific, have been handled using the compatible. This is all
very arbitrary, and can be discussed.
Thanks,
Miquèl
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
---
Changes in v4:
- Drop two binding patches judged useless.
- Collected Rob's acks.
- Fixed the RZ/N1D400 DTSI (removed the properties no longer relevant
after my binding changes).
- Link to v3: https://lore.kernel.org/r/20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com
Changes in v3:
- Collected tags from Wolfram and Geert.
- Dropped the Cadence compatible as this fallback would simply not work
alone.
- Fixed the clock issue reported by Santhosh.
- Fixed the DT snippet following the discussion with Geert.
- Modified more deeply the binding, to no longer expect a fifo
size/depth nor any trigger address, as these values have no meaning in
the score of the Renesas implementation.
- Link to v2: https://lore.kernel.org/r/20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com
Changes in v2:
- Fix commit log of DT binding patch, following Krzysztof's comment.
- Fix properties order in DTSI.
- Rebase on top of spi/for-next and fix all conflicts.
- Simplify even further the code in the cleanup patches following
Pratyush's advices.
- Link to v1: https://lore.kernel.org/r/20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com
---
Miquel Raynal (Schneider Electric) (15):
spi: dt-bindings: cdns,qspi-nor: Drop label in example
spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
spi: cadence-qspi: Align definitions
spi: cadence-qspi: Fix style and improve readability
spi: cadence-qspi: Fix ORing style and alignments
spi: cadence-qspi: Remove an useless operation
spi: cadence-qspi: Make sure we filter out unsupported ops
spi: cadence-qspi: Fix probe error path and remove
spi: cadence-qspi: Try hard to disable the clocks
spi: cadence-qspi: Kill cqspi_jh7110_clk_init
spi: cadence-qspi: Add a flag for controllers without indirect access support
spi: cadence-qspi: Make sure write protection is disabled
spi: cadence-qspi: Use a default value for cdns,fifo-width
spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
ARM: dts: r9a06g032: Describe the QSPI controller
.../devicetree/bindings/spi/cdns,qspi-nor.yaml | 35 ++-
arch/arm/boot/dts/renesas/r9a06g032.dtsi | 12 +
drivers/spi/spi-cadence-quadspi.c | 279 ++++++++++-----------
3 files changed, 177 insertions(+), 149 deletions(-)
---
base-commit: 7a3f3fdb79a26125b38fb91b68dab298ca7b44e0
change-id: 20251219-schneider-6-19-rc1-qspi-7c3e1547af6d
Best regards,
--
Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Hello Miquel, On 22/01/26 20:43, Miquel Raynal (Schneider Electric) wrote: > Hello, > > This series adds support for the QSPI controller available on Renesas > RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last > SPI patch for details), but has been tested by Wolfram (thank you!) on > the DB board. > Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/ > > Adding support for this SoC required a few adaptations in the Cadence > QSPI driver. The bulk of the work is in the few last patches. Everything > else is just misc style fixes and improvements which bothered me while I > was wandering. > > In order to support all constraints, I sometimes used a new quirk (for > the write protection feature and the "no indirect mode"), and sometimes > used the compatible directly. The ones I thought might not be RZ/N1 > specific have been implemented under the form of a quirk, in order to > ease their reuse. The other adaptations, which I believe are more > Renesas specific, have been handled using the compatible. This is all > very arbitrary, and can be discussed. > > Thanks, > Miquèl > > Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com> Thank you for the series! Tested it on TI's AM62A SK (OSPI NAND flash) and AM62P SK (OSPI NOR flash). Tested-by: Santhosh Kumar K <s-k6@ti.com> > --- > Changes in v4: > - Drop two binding patches judged useless. > - Collected Rob's acks. > - Fixed the RZ/N1D400 DTSI (removed the properties no longer relevant > after my binding changes). > - Link to v3: https://lore.kernel.org/r/20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com > > Changes in v3: > - Collected tags from Wolfram and Geert. > - Dropped the Cadence compatible as this fallback would simply not work > alone. > - Fixed the clock issue reported by Santhosh. > - Fixed the DT snippet following the discussion with Geert. > - Modified more deeply the binding, to no longer expect a fifo > size/depth nor any trigger address, as these values have no meaning in > the score of the Renesas implementation. > - Link to v2: https://lore.kernel.org/r/20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com > > Changes in v2: > - Fix commit log of DT binding patch, following Krzysztof's comment. > - Fix properties order in DTSI. > - Rebase on top of spi/for-next and fix all conflicts. > - Simplify even further the code in the cleanup patches following > Pratyush's advices. > - Link to v1: https://lore.kernel.org/r/20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com > > --- > Miquel Raynal (Schneider Electric) (15): > spi: dt-bindings: cdns,qspi-nor: Drop label in example > spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list > spi: cadence-qspi: Align definitions > spi: cadence-qspi: Fix style and improve readability > spi: cadence-qspi: Fix ORing style and alignments > spi: cadence-qspi: Remove an useless operation > spi: cadence-qspi: Make sure we filter out unsupported ops > spi: cadence-qspi: Fix probe error path and remove > spi: cadence-qspi: Try hard to disable the clocks > spi: cadence-qspi: Kill cqspi_jh7110_clk_init > spi: cadence-qspi: Add a flag for controllers without indirect access support > spi: cadence-qspi: Make sure write protection is disabled > spi: cadence-qspi: Use a default value for cdns,fifo-width > spi: cadence-qspi: Add support for the Renesas RZ/N1 controller > ARM: dts: r9a06g032: Describe the QSPI controller > > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 35 ++- > arch/arm/boot/dts/renesas/r9a06g032.dtsi | 12 + > drivers/spi/spi-cadence-quadspi.c | 279 ++++++++++----------- > 3 files changed, 177 insertions(+), 149 deletions(-) > --- > base-commit: 7a3f3fdb79a26125b38fb91b68dab298ca7b44e0 > change-id: 20251219-schneider-6-19-rc1-qspi-7c3e1547af6d > > Best regards,
On Thu, 22 Jan 2026 16:13:25 +0100, Miquel Raynal (Schneider Electric) wrote:
> This series adds support for the QSPI controller available on Renesas
> RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
> SPI patch for details), but has been tested by Wolfram (thank you!) on
> the DB board.
> Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/
>
> Adding support for this SoC required a few adaptations in the Cadence
> QSPI driver. The bulk of the work is in the few last patches. Everything
> else is just misc style fixes and improvements which bothered me while I
> was wandering.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[01/15] spi: dt-bindings: cdns,qspi-nor: Drop label in example
commit: ade3f7f883723cca5e1c967e574680b410226566
[02/15] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
(no commit info)
[03/15] spi: cadence-qspi: Align definitions
commit: 9dfc9c1c830717686908e2c16867d8dfae5cf5e7
[04/15] spi: cadence-qspi: Fix style and improve readability
commit: aac733a9663682387013350b4470a81344960f5d
[05/15] spi: cadence-qspi: Fix ORing style and alignments
commit: ec2da8bb0bc518ca5458d36de9aeec493ed5a790
[06/15] spi: cadence-qspi: Remove an useless operation
commit: 453c5d60d896398c32854b683aff6d5b8386fa03
[07/15] spi: cadence-qspi: Make sure we filter out unsupported ops
commit: bee085476d277e1f993cdec57e3c730f536594f0
[08/15] spi: cadence-qspi: Fix probe error path and remove
commit: f18c8cfa4f1af2cf7d68d86989a7d6109acfa1bb
[09/15] spi: cadence-qspi: Try hard to disable the clocks
commit: 612227b392eed94a3398dc03334a84a699a82276
[10/15] spi: cadence-qspi: Kill cqspi_jh7110_clk_init
(no commit info)
[11/15] spi: cadence-qspi: Add a flag for controllers without indirect access support
commit: ae62e7cf6ab52cebc83feb0bcb374082eaabbf5e
[12/15] spi: cadence-qspi: Make sure write protection is disabled
commit: 590f2430733f1302a78ac405370b8f01038adbf5
[13/15] spi: cadence-qspi: Use a default value for cdns,fifo-width
commit: 77ee3ba5d4152f01ba4674b0e0ae51f8a51250bf
[14/15] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
(no commit info)
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
Hi Mark, > Applied to > > https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next > > Thanks! [...] > [02/15] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list > (no commit info) > [10/15] spi: cadence-qspi: Kill cqspi_jh7110_clk_init > (no commit info) > [14/15] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller > (no commit info) Git was actually smart enough, it solved the conflicts without asking during rebase :) Shall I resend these 3 patches (+ the typo reported by Geert) updated after a spi/for-next rebase or do you prefer to wait for next -rc1? Thanks, Miquèl
On Thu, Feb 05, 2026 at 10:16:01AM +0100, Miquel Raynal wrote: > Hi Mark, > > [02/15] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list > > (no commit info) > > [10/15] spi: cadence-qspi: Kill cqspi_jh7110_clk_init > > (no commit info) > > [14/15] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller > > (no commit info) > Git was actually smart enough, it solved the conflicts without asking > during rebase :) Shall I resend these 3 patches (+ the typo reported by > Geert) updated after a spi/for-next rebase or do you prefer to wait for > next -rc1? Sure, resending now is fine.
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