This series addresses multi-function endpoint configuration issues in
the DWC PCIe controller driver. The changes enable proper operations
for physical functions and enhance the multi-function endpoint support.

Aksh Garg (2):
  PCI: dwc: ep: Fix resizable BAR support for multi-PF configurations
  PCI: dwc: ep: Add per-PF BAR and iATU mapping support

 .../pci/controller/dwc/pcie-designware-ep.c   | 97 +++++++++++++------
 drivers/pci/controller/dwc/pcie-designware.h  |  4 +-
 2 files changed, 69 insertions(+), 32 deletions(-)

-- 
2.34.1

On Wed, Jan 21, 2026 at 11:12:12AM +0530, Aksh Garg wrote:
> This series addresses multi-function endpoint configuration issues in
> the DWC PCIe controller driver. The changes enable proper operations
> for physical functions and enhance the multi-function endpoint support.


Considering that the DWC driver design has always been broken with regards
to multiple physical functions, as you explain yourself, the iATU to BAR
mapping has always been per controller, not per PF.

Thus, it would be nice if you explained how you have actually tested this.

Does the controller you are using have both Resizable and Programmable BARs?


Kind regards,
Niklas

On Wed, Jan 21, 2026 at 09:50:58AM +0100, Niklas Cassel wrote:
> On Wed, Jan 21, 2026 at 11:12:12AM +0530, Aksh Garg wrote:
> > This series addresses multi-function endpoint configuration issues in
> > the DWC PCIe controller driver. The changes enable proper operations
> > for physical functions and enhance the multi-function endpoint support.
> 
> 
> Considering that the DWC driver design has always been broken with regards
> to multiple physical functions, as you explain yourself, the iATU to BAR
> mapping has always been per controller, not per PF.
> 
> Thus, it would be nice if you explained how you have actually tested this.
> 
> Does the controller you are using have both Resizable and Programmable BARs?

If your PCIe controller supports multiple PFs, as you might know,
while:

const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
                                                       u8 func_no, u8 vfunc_no);

takes both a PF and a VF...

dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
ignores both of these parameters and simply call:
ep->ops->get_features(ep);


For each PF in your controller, do all BARs have the exact same definition?

e.g. all BARs for each PF would need to have the same type, e.g. if BAR0
is FIXED, BAR1 is programmable, and BAR2 is resizable, with the current
design of dw_pcie_ep_get_features() that would need to be the case for all
PFs.


Kind regards,
Niklas

Hi Niklas, Thanks a lot for your comments and reviews!

> On Wed, Jan 21, 2026 at 09:50:58AM +0100, Niklas Cassel wrote:
>> On Wed, Jan 21, 2026 at 11:12:12AM +0530, Aksh Garg wrote:
>> > This series addresses multi-function endpoint configuration issues in
>> > the DWC PCIe controller driver. The changes enable proper operations
>> > for physical functions and enhance the multi-function endpoint support.
>> 
>> 
>> Considering that the DWC driver design has always been broken with regards
>> to multiple physical functions, as you explain yourself, the iATU to BAR
>> mapping has always been per controller, not per PF.
>> 
>> Thus, it would be nice if you explained how you have actually tested this.
>> 
>> Does the controller you are using have both Resizable and Programmable BARs?
> 
> If your PCIe controller supports multiple PFs, as you might know,
> while:
> 
> const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
>                                                         u8 func_no, u8 vfunc_no);
> 
> takes both a PF and a VF...
> 
> dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
> ignores both of these parameters and simply call:
> ep->ops->get_features(ep);
> 
> 
> For each PF in your controller, do all BARs have the exact same definition?

All the BARs of all the PFs in my controller are resizable, hence can 
have the same features structure.

However, this might need a fix as well if a controller comes out to have 
different BAR definitions for different PFs!

Regards,
Aksh Garg

> 
> e.g. all BARs for each PF would need to have the same type, e.g. if BAR0
> is FIXED, BAR1 is programmable, and BAR2 is resizable, with the current
> design of dw_pcie_ep_get_features() that would need to be the case for all
> PFs. >
> Kind regards,
> Niklas
>