That peripheral clock is required for proper OTPC function.
Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- no changes
v2:
- new patch in series, was not present in v1
drivers/clk/at91/sam9x60.c | 1 +
drivers/clk/at91/sam9x7.c | 1 +
drivers/clk/at91/sama7d65.c | 1 +
drivers/clk/at91/sama7g5.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index a9f293a8e3b26..11f16126ff9e9 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -146,6 +146,7 @@ static const struct {
{ .n = "isi_clk", .id = 43, },
{ .n = "pioD_clk", .id = 44, },
{ .n = "tcb1_clk", .id = 45, },
+ { .n = "otpc_clk", .id = 46, },
{ .n = "dbgu_clk", .id = 47, },
/*
* mpddr_clk feeds DDR controller and is enabled by bootloader thus we
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
index 9a5afd258cb86..c4d2b022d9d07 100644
--- a/drivers/clk/at91/sam9x7.c
+++ b/drivers/clk/at91/sam9x7.c
@@ -407,6 +407,7 @@ static const struct {
{ .n = "isi_clk", .id = 43, },
{ .n = "pioD_clk", .id = 44, },
{ .n = "tcb1_clk", .id = 45, },
+ { .n = "otpc_clk", .id = 46, },
{ .n = "dbgu_clk", .id = 47, },
{ .n = "pmecc_clk", .id = 48, },
/*
diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index 5d8973aa50a53..52467d629258f 100644
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -641,6 +641,7 @@ static struct {
{ .n = "mcan2_clk", .p = PCK_PARENT_HW_MCK5, .id = 60, .r = { .max = 200000000, }, },
{ .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK5, .id = 61, .r = { .max = 200000000, }, },
{ .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK5, .id = 62, .r = { .max = 200000000, }, },
+ { .n = "otpc_clk", .p = PCK_PARENT_HW_MCK0, .id = 63, },
{ .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK9, .id = 64, .r = { .max = 200000000, }, },
{ .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK9, .id = 65, .r = { .max = 200000000, }, },
{ .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK7, .id = 66, },
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 9a6f0f30b2b7e..3e0cfd2613851 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -504,6 +504,7 @@ static struct {
{ .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK1, .id = 64, .r = { .max = 200000000, }, },
{ .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK1, .id = 65, .r = { .max = 200000000, }, },
{ .n = "mcan5_clk", .p = PCK_PARENT_HW_MCK1, .id = 66, .r = { .max = 200000000, }, },
+ { .n = "otpc_clk", .p = PCK_PARENT_HW_MCK0, .id = 67, },
{ .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 68, .r = { .max = 200000000, }, },
{ .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 69, .r = { .max = 200000000, }, },
{ .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK1, .id = 70, },
--
2.47.3The SAM9X60 SoC family has a similar, but slightly different OTPC to the
SAMA7G5 family.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Notes:
v3:
- Added Acked-by trailer
v2:
- Fix dt_binding_check warnings
.../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
index cc25f2927682e..9a7aaf64eef32 100644
--- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
+++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@@ -21,7 +21,9 @@ allOf:
properties:
compatible:
items:
- - const: microchip,sama7g5-otpc
+ - enum:
+ - microchip,sam9x60-otpc
+ - microchip,sama7g5-otpc
- const: syscon
reg:
--
2.47.3The OTPC requires both the peripheral clock through PMC and the main RC
oscillator. Seemed to work without explicitly enabling those clocks on
sama7g5 before, but did not on sam9x60.
Older datasheets were not clear and explicit about this, but recent are,
e.g. SAMA7G5 series datasheet (DS60001765B),
section 30.4.1 Power Management:
> The OTPC is clocked through the Power Management Controller (PMC).
> The user must power on the main RC oscillator and enable the
> peripheral clock of the OTPC prior to reading or writing the OTP
> memory.
Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Removed clock-names (led to confusion, and not used by the driver anyways)
- Removed redundant example
v2:
- new patch, not present in v1
.../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
index 9a7aaf64eef32..847dfb67c6b72 100644
--- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
+++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@@ -29,6 +29,11 @@ properties:
reg:
maxItems: 1
+ clocks:
+ items:
+ - description: main rc oscillator
+ - description: otpc peripheral clock
+
required:
- compatible
- reg
@@ -37,6 +42,8 @@ unevaluatedProperties: false
examples:
- |
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/clock/microchip,sama7g5-pmc.h>
#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
otpc: efuse@e8c00000 {
@@ -44,6 +51,7 @@ examples:
reg = <0xe8c00000 0xec>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 67>;
temperature_calib: calib@1 {
reg = <OTP_PKT(1) 76>;
--
2.47.3
On 1/20/26 17:44, Alexander Dahl wrote:
> The OTPC requires both the peripheral clock through PMC and the main RC
> oscillator. Seemed to work without explicitly enabling those clocks on
> sama7g5 before, but did not on sam9x60.
>
> Older datasheets were not clear and explicit about this, but recent are,
> e.g. SAMA7G5 series datasheet (DS60001765B),
> section 30.4.1 Power Management:
>
>> The OTPC is clocked through the Power Management Controller (PMC).
>> The user must power on the main RC oscillator and enable the
>> peripheral clock of the OTPC prior to reading or writing the OTP
>> memory.
As this was not mentioned in the previous datasheet versions, the current driver
don't handle those clocks, and it probably worked as the clocks were enabled by
bootloaders, I think the clocks should be marked as required and this patch to
be propagated as a fix along with fixes on driver and device trees.
I'll let DT binding maintainers for the final decision on this.
>
> Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
Why this link here?
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
> ---
>
> Notes:
> v3:
> - Removed clock-names (led to confusion, and not used by the driver anyways)
> - Removed redundant example
>
> v2:
> - new patch, not present in v1
>
> .../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
> index 9a7aaf64eef32..847dfb67c6b72 100644
> --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
> @@ -29,6 +29,11 @@ properties:
> reg:
> maxItems: 1
>
> + clocks:
> + items:
> + - description: main rc oscillator
> + - description: otpc peripheral clock
> +
> required:
> - compatible
> - reg
> @@ -37,6 +42,8 @@ unevaluatedProperties: false
>
> examples:
> - |
> + #include <dt-bindings/clock/at91.h>
> + #include <dt-bindings/clock/microchip,sama7g5-pmc.h>
> #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
>
> otpc: efuse@e8c00000 {
> @@ -44,6 +51,7 @@ examples:
> reg = <0xe8c00000 0xec>;
> #address-cells = <1>;
> #size-cells = <1>;
> + clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 67>;
>
> temperature_calib: calib@1 {
> reg = <OTP_PKT(1) 76>;
On 1/31/26 17:47, Claudiu Beznea wrote:
>
>
> On 1/20/26 17:44, Alexander Dahl wrote:
>> The OTPC requires both the peripheral clock through PMC and the main RC
>> oscillator. Seemed to work without explicitly enabling those clocks on
>> sama7g5 before, but did not on sam9x60.
>>
>> Older datasheets were not clear and explicit about this, but recent are,
>> e.g. SAMA7G5 series datasheet (DS60001765B),
>> section 30.4.1 Power Management:
>>
>>> The OTPC is clocked through the Power Management Controller (PMC).
>>> The user must power on the main RC oscillator and enable the
>>> peripheral clock of the OTPC prior to reading or writing the OTP
>>> memory.
>
> As this was not mentioned in the previous datasheet versions, the current driver
> don't handle those clocks, and it probably worked as the clocks were enabled by
> bootloaders, I think the clocks should be marked as required and this patch to
> be propagated as a fix along with fixes on driver and device trees.
Ah, wait, you can't propagate it as a fix as you don't have the necessary clocks
exported in device tree in the older kernels. And you are just handling it in
this series.
>
> I'll let DT binding maintainers for the final decision on this.
>
>>
>> Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-
>> b5d8-6e2fd5e08c28@microchip.com/T/#u
>
> Why this link here?
>
>> Signed-off-by: Alexander Dahl <ada@thorsis.com>
>> ---
>>
>> Notes:
>> v3:
>> - Removed clock-names (led to confusion, and not used by the driver anyways)
>> - Removed redundant example
>> v2:
>> - new patch, not present in v1
>>
>> .../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-
>> otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
>> index 9a7aaf64eef32..847dfb67c6b72 100644
>> --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
>> +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
>> @@ -29,6 +29,11 @@ properties:
>> reg:
>> maxItems: 1
>> + clocks:
>> + items:
>> + - description: main rc oscillator
>> + - description: otpc peripheral clock
>> +
>> required:
>> - compatible
>> - reg
>> @@ -37,6 +42,8 @@ unevaluatedProperties: false
>> examples:
>> - |
>> + #include <dt-bindings/clock/at91.h>
>> + #include <dt-bindings/clock/microchip,sama7g5-pmc.h>
>> #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
>> otpc: efuse@e8c00000 {
>> @@ -44,6 +51,7 @@ examples:
>> reg = <0xe8c00000 0xec>;
>> #address-cells = <1>;
>> #size-cells = <1>;
>> + clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MAIN_RC>, <&pmc
>> PMC_TYPE_PERIPHERAL 67>;
>> temperature_calib: calib@1 {
>> reg = <OTP_PKT(1) 76>;
>
On Tue, 20 Jan 2026 16:44:43 +0100, Alexander Dahl wrote:
> The OTPC requires both the peripheral clock through PMC and the main RC
> oscillator. Seemed to work without explicitly enabling those clocks on
> sama7g5 before, but did not on sam9x60.
>
> Older datasheets were not clear and explicit about this, but recent are,
> e.g. SAMA7G5 series datasheet (DS60001765B),
> section 30.4.1 Power Management:
>
> > The OTPC is clocked through the Power Management Controller (PMC).
> > The user must power on the main RC oscillator and enable the
> > peripheral clock of the OTPC prior to reading or writing the OTP
> > memory.
>
> Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
> ---
>
> Notes:
> v3:
> - Removed clock-names (led to confusion, and not used by the driver anyways)
> - Removed redundant example
>
> v2:
> - new patch, not present in v1
>
> .../devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.example.dts:19:18: fatal error: dt-bindings/clock/microchip,sama7g5-pmc.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,sama7g5-pmc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:141: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1559: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260120154502.1280938-3-ada@thorsis.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
The OTPC Control Register (OTPC_CR) has just write-only members.
Reading from that register leads to a warning in OTPC Write Protection
Status Register (OTPC_WPSR) in field Software Error Type (SWETYP) of
type READ_WO (A write-only register has been read (warning).)
Just create the register write content from scratch is sufficient here.
Fixes: 98830350d3fc ("nvmem: microchip-otpc: add support")
Cc: stable@vger.kernel.org
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Reorder tags
- Add stable tag
v2:
- Add Fixes tag
- Remove temporary variable usage
- Reword misleading subject (s/writing/reading/)
drivers/nvmem/microchip-otpc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index df979e8549fdb..e2851c63cc0b4 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -82,9 +82,7 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR);
/* Set read. */
- tmp = readl_relaxed(otpc->base + MCHP_OTPC_CR);
- tmp |= MCHP_OTPC_CR_READ;
- writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR);
+ writel_relaxed(MCHP_OTPC_CR_READ, otpc->base + MCHP_OTPC_CR);
/* Wait for packet to be transferred into temporary buffers. */
return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ),
--
2.47.3
On 1/20/26 17:44, Alexander Dahl wrote:
> The OTPC Control Register (OTPC_CR) has just write-only members.
> Reading from that register leads to a warning in OTPC Write Protection
> Status Register (OTPC_WPSR) in field Software Error Type (SWETYP) of
> type READ_WO (A write-only register has been read (warning).)
>
> Just create the register write content from scratch is sufficient here.
>
> Fixes: 98830350d3fc ("nvmem: microchip-otpc: add support")
> Cc:stable@vger.kernel.org
> Signed-off-by: Alexander Dahl<ada@thorsis.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Makes no sense to have a timeout shorter than the sleep time, it would
run into timeout right after the first sleep already.
While at it, use a more specific macro instead of the generic one, which
does exactly the same, but needs less parameters.
Fixes: 98830350d3fc ("nvmem: microchip-otpc: add support")
Cc: stable@vger.kernel.org
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Reorder tags
- Add stable tag
v2:
- Add Fixes tag
drivers/nvmem/microchip-otpc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index e2851c63cc0b4..bf7e5167152cb 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -85,8 +85,8 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
writel_relaxed(MCHP_OTPC_CR_READ, otpc->base + MCHP_OTPC_CR);
/* Wait for packet to be transferred into temporary buffers. */
- return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ),
- 10000, 2000, false, otpc->base + MCHP_OTPC_SR);
+ return readl_relaxed_poll_timeout(otpc->base + MCHP_OTPC_SR, tmp,
+ !(tmp & MCHP_OTPC_SR_READ), 2000, 10000);
}
/*
--
2.47.3
On 1/20/26 17:44, Alexander Dahl wrote:
> Makes no sense to have a timeout shorter than the sleep time, it would
> run into timeout right after the first sleep already.
> While at it, use a more specific macro instead of the generic one, which
> does exactly the same, but needs less parameters.
>
> Fixes: 98830350d3fc ("nvmem: microchip-otpc: add support")
> Cc:stable@vger.kernel.org
> Signed-off-by: Alexander Dahl<ada@thorsis.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Register layout is almost identical to SAMA7G5 OTPC. SAMA7G5 has some
additional bits in common registers, and some additional registers all
related to custom packages in secure world. None of these are currently
used by the driver.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- no changes
v2:
- Reword commit message (additional information about SoC differences)
drivers/nvmem/microchip-otpc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index bf7e5167152cb..d39f2d57e5f5e 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -269,6 +269,7 @@ static int mchp_otpc_probe(struct platform_device *pdev)
static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {
{ .compatible = "microchip,sama7g5-otpc", },
+ { .compatible = "microchip,sam9x60-otpc", },
{ },
};
MODULE_DEVICE_TABLE(of, mchp_otpc_ids);
--
2.47.3
On 1/20/26 17:44, Alexander Dahl wrote:
> Register layout is almost identical to SAMA7G5 OTPC. SAMA7G5 has some
Can't you just use a fallback to sama7g5 for sam9x60 and drop this patch?
> additional bits in common registers, and some additional registers all
> related to custom packages in secure world. None of these are currently
> used by the driver.
>
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
> ---
>
> Notes:
> v3:
> - no changes
>
> v2:
> - Reword commit message (additional information about SoC differences)
>
> drivers/nvmem/microchip-otpc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
> index bf7e5167152cb..d39f2d57e5f5e 100644
> --- a/drivers/nvmem/microchip-otpc.c
> +++ b/drivers/nvmem/microchip-otpc.c
> @@ -269,6 +269,7 @@ static int mchp_otpc_probe(struct platform_device *pdev)
>
> static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {
> { .compatible = "microchip,sama7g5-otpc", },
> + { .compatible = "microchip,sam9x60-otpc", },
> { },
> };
> MODULE_DEVICE_TABLE(of, mchp_otpc_ids);
Without enabling the main rc clock, initializing the packet list leads
to a read timeout on the first packet, at least on sam9x60.
According to SAM9X60 datasheet (DS60001579G) section "23.4 Product
Dependencies" the clock must be enabled for reading and writing.
Tested on sam9x60-curiosity board.
Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Rewrap lines
v2:
- Rewrite to enable _all_ clocks defined in dts
drivers/nvmem/microchip-otpc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index d39f2d57e5f5e..34c0d7611f3e4 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -8,6 +8,7 @@
*/
#include <linux/bitfield.h>
+#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
@@ -241,6 +242,7 @@ static struct nvmem_config mchp_nvmem_config = {
static int mchp_otpc_probe(struct platform_device *pdev)
{
struct nvmem_device *nvmem;
+ struct clk_bulk_data *clks;
struct mchp_otpc *otpc;
u32 size;
int ret;
@@ -253,6 +255,10 @@ static int mchp_otpc_probe(struct platform_device *pdev)
if (IS_ERR(otpc->base))
return PTR_ERR(otpc->base);
+ ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "Error getting clocks!\n");
+
otpc->dev = &pdev->dev;
ret = mchp_otpc_init_packets_list(otpc, &size);
if (ret)
--
2.47.3
On 1/20/26 17:44, Alexander Dahl wrote:
> Without enabling the main rc clock, initializing the packet list leads
> to a read timeout on the first packet, at least on sam9x60.
>
> According to SAM9X60 datasheet (DS60001579G) section "23.4 Product
> Dependencies" the clock must be enabled for reading and writing.
>
> Tested on sam9x60-curiosity board.
>
> Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
Why this link here?
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> ---
>
> Notes:
> v3:
> - Rewrap lines
>
> v2:
> - Rewrite to enable _all_ clocks defined in dts
>
> drivers/nvmem/microchip-otpc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
> index d39f2d57e5f5e..34c0d7611f3e4 100644
> --- a/drivers/nvmem/microchip-otpc.c
> +++ b/drivers/nvmem/microchip-otpc.c
> @@ -8,6 +8,7 @@
> */
>
> #include <linux/bitfield.h>
> +#include <linux/clk.h>
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/nvmem-provider.h>
> @@ -241,6 +242,7 @@ static struct nvmem_config mchp_nvmem_config = {
> static int mchp_otpc_probe(struct platform_device *pdev)
> {
> struct nvmem_device *nvmem;
> + struct clk_bulk_data *clks;
> struct mchp_otpc *otpc;
> u32 size;
> int ret;
> @@ -253,6 +255,10 @@ static int mchp_otpc_probe(struct platform_device *pdev)
> if (IS_ERR(otpc->base))
> return PTR_ERR(otpc->base);
>
> + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clks);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret, "Error getting clocks!\n");
> +
> otpc->dev = &pdev->dev;
> ret = mchp_otpc_init_packets_list(otpc, &size);
> if (ret)
For SAM9X60 the Product UID x Register containing the Unique Product ID
is part of the OTPC registers. We have everything at hand here to just
create a trivial nvmem device for those.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- no changes
v2:
- Use dev_err_probe() for error reporting (thanks Claudiu)
- Move required register definition over here from removed patch
drivers/nvmem/microchip-otpc.c | 38 +++++++++++++++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index 34c0d7611f3e4..b35ed13b004bb 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -25,10 +25,14 @@
#define MCHP_OTPC_HR (0x20)
#define MCHP_OTPC_HR_SIZE GENMASK(15, 8)
#define MCHP_OTPC_DR (0x24)
+#define MCHP_OTPC_UID0R (0x60)
#define MCHP_OTPC_NAME "mchp-otpc"
#define MCHP_OTPC_SIZE (11 * 1024)
+#define MCHP_OTPC_UID_NAME "mchp-uid"
+#define MCHP_OTPC_UID_SIZE 16
+
/**
* struct mchp_otpc - OTPC private data structure
* @base: base address
@@ -230,6 +234,16 @@ static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
return 0;
}
+static int mchp_otpc_uid_read(void *priv, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct mchp_otpc *otpc = priv;
+
+ memcpy_fromio(val, otpc->base + MCHP_OTPC_UID0R + offset, bytes);
+
+ return 0;
+}
+
static struct nvmem_config mchp_nvmem_config = {
.name = MCHP_OTPC_NAME,
.type = NVMEM_TYPE_OTP,
@@ -239,6 +253,15 @@ static struct nvmem_config mchp_nvmem_config = {
.reg_read = mchp_otpc_read,
};
+static struct nvmem_config mchp_otpc_uid_nvmem_config = {
+ .name = MCHP_OTPC_UID_NAME,
+ .read_only = true,
+ .word_size = 4,
+ .stride = 4,
+ .size = MCHP_OTPC_UID_SIZE,
+ .reg_read = mchp_otpc_uid_read,
+};
+
static int mchp_otpc_probe(struct platform_device *pdev)
{
struct nvmem_device *nvmem;
@@ -269,8 +292,21 @@ static int mchp_otpc_probe(struct platform_device *pdev)
mchp_nvmem_config.size = size;
mchp_nvmem_config.priv = otpc;
nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config);
+ if (IS_ERR(nvmem)) {
+ return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
+ "Error registering OTP as nvmem device\n");
+ }
- return PTR_ERR_OR_ZERO(nvmem);
+ mchp_otpc_uid_nvmem_config.dev = otpc->dev;
+ mchp_otpc_uid_nvmem_config.priv = otpc;
+
+ nvmem = devm_nvmem_register(&pdev->dev, &mchp_otpc_uid_nvmem_config);
+ if (IS_ERR(nvmem)) {
+ return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
+ "Error registering UIDxR as nvmem device\n");
+ }
+
+ return 0;
}
static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {
--
2.47.3
On 1/20/26 17:44, Alexander Dahl wrote:
> For SAM9X60 the Product UID x Register containing the Unique Product ID
> is part of the OTPC registers.
SAMA7G5 as well.
> We have everything at hand here to just
> create a trivial nvmem device for those.
Please massage a bit the patch description to match
https://www.kernel.org/doc/html/v6.13/process/submitting-patches.html#describe-your-changes
>
> Signed-off-by: Alexander Dahl <ada@thorsis.com>
> ---
>
> Notes:
> v3:
> - no changes
>
> v2:
> - Use dev_err_probe() for error reporting (thanks Claudiu)
> - Move required register definition over here from removed patch
>
> drivers/nvmem/microchip-otpc.c | 38 +++++++++++++++++++++++++++++++++-
> 1 file changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
> index 34c0d7611f3e4..b35ed13b004bb 100644
> --- a/drivers/nvmem/microchip-otpc.c
> +++ b/drivers/nvmem/microchip-otpc.c
> @@ -25,10 +25,14 @@
> #define MCHP_OTPC_HR (0x20)
> #define MCHP_OTPC_HR_SIZE GENMASK(15, 8)
> #define MCHP_OTPC_DR (0x24)
> +#define MCHP_OTPC_UID0R (0x60)
>
> #define MCHP_OTPC_NAME "mchp-otpc"
> #define MCHP_OTPC_SIZE (11 * 1024)
>
> +#define MCHP_OTPC_UID_NAME "mchp-uid"
> +#define MCHP_OTPC_UID_SIZE 16
I think you can drop these as they are used (individually) in a single place.
> +
> /**
> * struct mchp_otpc - OTPC private data structure
> * @base: base address
> @@ -230,6 +234,16 @@ static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
> return 0;
> }
>
> +static int mchp_otpc_uid_read(void *priv, unsigned int offset,
> + void *val, size_t bytes)
> +{
> + struct mchp_otpc *otpc = priv;
> +
> + memcpy_fromio(val, otpc->base + MCHP_OTPC_UID0R + offset, bytes);
Include <asm-generic/logic_io.h> for this one?
> +
> + return 0;
> +}
> +
> static struct nvmem_config mchp_nvmem_config = {
> .name = MCHP_OTPC_NAME,
> .type = NVMEM_TYPE_OTP,
> @@ -239,6 +253,15 @@ static struct nvmem_config mchp_nvmem_config = {
> .reg_read = mchp_otpc_read,
> };
>
> +static struct nvmem_config mchp_otpc_uid_nvmem_config = {
> + .name = MCHP_OTPC_UID_NAME,
Should the type be filled here?
> + .read_only = true,
> + .word_size = 4,
> + .stride = 4,
> + .size = MCHP_OTPC_UID_SIZE,
> + .reg_read = mchp_otpc_uid_read,
> +};
> +
> static int mchp_otpc_probe(struct platform_device *pdev)
> {
> struct nvmem_device *nvmem;
> @@ -269,8 +292,21 @@ static int mchp_otpc_probe(struct platform_device *pdev)
> mchp_nvmem_config.size = size;
> mchp_nvmem_config.priv = otpc;
> nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config);
> + if (IS_ERR(nvmem)) {
> + return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
> + "Error registering OTP as nvmem device\n");
> + }
>
> - return PTR_ERR_OR_ZERO(nvmem);
> + mchp_otpc_uid_nvmem_config.dev = otpc->dev;
> + mchp_otpc_uid_nvmem_config.priv = otpc;
> +
> + nvmem = devm_nvmem_register(&pdev->dev, &mchp_otpc_uid_nvmem_config);
> + if (IS_ERR(nvmem)) {
> + return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
> + "Error registering UIDxR as nvmem device\n");
> + }
> +
> + return 0;
> }
>
> static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {
The bindings were split up per SoC before adding new members for
missing clocks.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- extend to all at91 family SoCs
v2:
- new patch, not present in v1
arch/arm/boot/dts/microchip/at91rm9200.dtsi | 3 ++-
arch/arm/boot/dts/microchip/at91sam9260.dtsi | 19 ++++++++-------
arch/arm/boot/dts/microchip/at91sam9261.dtsi | 7 +++---
arch/arm/boot/dts/microchip/at91sam9263.dtsi | 9 +++----
arch/arm/boot/dts/microchip/at91sam9g45.dtsi | 11 +++++----
arch/arm/boot/dts/microchip/at91sam9n12.dtsi | 7 +++---
arch/arm/boot/dts/microchip/at91sam9rl.dtsi | 9 +++----
arch/arm/boot/dts/microchip/at91sam9x5.dtsi | 11 +++++----
arch/arm/boot/dts/microchip/sam9x60.dtsi | 15 ++++++------
arch/arm/boot/dts/microchip/sam9x7.dtsi | 13 +++++-----
arch/arm/boot/dts/microchip/sama5d2.dtsi | 25 ++++++++++----------
arch/arm/boot/dts/microchip/sama5d3.dtsi | 9 +++----
arch/arm/boot/dts/microchip/sama5d4.dtsi | 9 +++----
arch/arm/boot/dts/microchip/sama7d65.dtsi | 15 ++++++------
arch/arm/boot/dts/microchip/sama7g5.dtsi | 23 +++++++++---------
15 files changed, 100 insertions(+), 85 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi
index e105ad855ce8b..f158c1d70ac2d 100644
--- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91rm9200-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -601,7 +602,7 @@ dbgu: serial@fffff200 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91RM9200_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi
index fc0b6a73204f8..76184155e6746 100644
--- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9260-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -127,20 +128,20 @@ pmc: clock-controller@fffffc00 {
reset-controller@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_SLOW>;
};
shdwc: poweroff@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_SLOW>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
};
tcb0: timer@fffa0000 {
@@ -151,7 +152,7 @@ tcb0: timer@fffa0000 {
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -163,7 +164,7 @@ tcb1: timer@fffdc000 {
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>,
<27 IRQ_TYPE_LEVEL_HIGH 0>,
<28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -537,7 +538,7 @@ dbgu: serial@fffff200 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -720,7 +721,7 @@ rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_SLOW>;
status = "disabled";
};
@@ -728,7 +729,7 @@ watchdog: watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_SLOW>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -766,7 +767,7 @@ ebi: ebi@10000000 {
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/microchip/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi
index d1d678b77e84b..57643738b7c9a 100644
--- a/arch/arm/boot/dts/microchip/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9260-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -112,7 +113,7 @@ ebi: ebi@10000000 {
0x5 0x0 0x60000000 0x10000000
0x6 0x0 0x70000000 0x10000000
0x7 0x0 0x80000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -309,7 +310,7 @@ dbgu: serial@fffff200 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -624,7 +625,7 @@ pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
};
rtc@fffffd20 {
diff --git a/arch/arm/boot/dts/microchip/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi
index a4b5d1f228f9c..48feaa2415bb6 100644
--- a/arch/arm/boot/dts/microchip/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9263.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9260-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -139,7 +140,7 @@ pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
};
tcb0: timer@fff7c000 {
@@ -545,7 +546,7 @@ dbgu: serial@ffffee00 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -790,7 +791,7 @@ ebi0: ebi@10000000 {
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
status = "disabled";
nand_controller0: nand-controller {
@@ -811,7 +812,7 @@ ebi1: ebi@70000000 {
reg = <0x80000000 0x20000000>;
ranges = <0x0 0x0 0x80000000 0x10000000
0x1 0x0 0x90000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9260_PMC_MCK>;
status = "disabled";
nand_controller1: nand-controller {
diff --git a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi
index 4e00ed2d3ecdf..73c188ca97f4a 100644
--- a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9g45-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -148,7 +149,7 @@ pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9G45_PMC_MCK>;
};
@@ -681,7 +682,7 @@ dbgu: serial@ffffee00 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9G45_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -918,7 +919,7 @@ usb2: gadget@fff78000 {
reg = <0x00600000 0x80000
0xfff78000 0x400>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE AT91SAM9G45_PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -977,7 +978,7 @@ usb1: usb@800000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9G45_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -995,7 +996,7 @@ ebi: ebi@10000000 {
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9G45_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi
index af41c3dbb4bfb..ee7027387292f 100644
--- a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9n12-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -137,7 +138,7 @@ pit: timer@fffffe30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9N12_PMC_MCK>;
};
poweroff@fffffe10 {
@@ -581,7 +582,7 @@ dbgu: serial@fffff200 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9N12_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -770,7 +771,7 @@ ebi: ebi@10000000 {
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9N12_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi
index de74cf2980a04..78ede09d34861 100644
--- a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9rl-pmc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
@@ -112,7 +113,7 @@ ebi: ebi@10000000 {
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9RL_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -287,7 +288,7 @@ usb0: gadget@fffd4000 {
reg = <0x00600000 0x100000>,
<0xfffd4000 0x4000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE AT91SAM9RL_PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -331,7 +332,7 @@ dbgu: serial@fffff200 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9RL_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -788,7 +789,7 @@ pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9RL_PMC_MCK>;
};
watchdog@fffffd40 {
diff --git a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi
index 9070fd06995a0..e1ba217b5d624 100644
--- a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,at91sam9x5-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -151,7 +152,7 @@ pit: timer@fffffe30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9X5_PMC_MCK>;
};
clk32k: clock-controller@fffffe50 {
@@ -682,7 +683,7 @@ dbgu: serial@fffff200 {
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
<&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9X5_PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -852,7 +853,7 @@ usb2: gadget@f803c000 {
reg = <0x00500000 0x80000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9X5_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -899,7 +900,7 @@ usb1: usb@700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9X5_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -917,7 +918,7 @@ ebi: ebi@10000000 {
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE AT91SAM9X5_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index b075865e6a768..f9e3962faca3f 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/microchip,sam9x60-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
@@ -81,9 +82,9 @@ usb0: gadget@500000 {
reg = <0x00500000 0x100000
0xf803c000 0x400>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>;
clock-names = "pclk", "hclk";
- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
@@ -101,9 +102,9 @@ usb2: usb@700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_UTMI>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
@@ -121,7 +122,7 @@ ebi: ebi@10000000 {
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -1063,7 +1064,7 @@ hlcdc: hlcdc@f8038000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
clock-names = "periph_clk","sys_clk", "slow_clk";
assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MCK>;
status = "disabled";
hlcdc-display-controller {
@@ -1369,7 +1370,7 @@ pit: timer@fffffe40 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MCK>;
};
clk32k: clock-controller@fffffe50 {
diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi
index 46dacbbd201dd..69d51bd352bb0 100644
--- a/arch/arm/boot/dts/microchip/sam9x7.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi
@@ -8,6 +8,7 @@
*/
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/microchip,sam9x7-pmc.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -288,7 +289,7 @@ AT91_XDMAC_DT_PERID(26))>,
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>;
clock-names = "pclk", "gclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 35>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_PLLADIV2>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X7_PMC_PLLADIV2>;
status = "disabled";
};
@@ -500,9 +501,9 @@ can0: can@f8000000 {
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
clock-names = "hclk", "cclk";
- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
+ assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
assigned-clock-rates = <480000000>, <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>;
bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -516,9 +517,9 @@ can1: can@f8004000 {
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
clock-names = "hclk", "cclk";
- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
+ assigned-clocks = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
assigned-clock-rates = <480000000>, <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>, <&pmc PMC_TYPE_CORE SAM9X7_PMC_UTMI>;
bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -1158,7 +1159,7 @@ pmecc: ecc-engine@ffffe000 {
mpddrc: mpddrc@ffffe800 {
compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc";
reg = <0xffffe800 0x200>;
- clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE SAM9X7_PMC_MCK>;
clock-names = "ddrck", "mpddr";
};
diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi
index fde890f18d201..343fd4e878055 100644
--- a/arch/arm/boot/dts/microchip/sama5d2.dtsi
+++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,sama5d2-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
@@ -47,7 +48,7 @@ etb@740000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x740000 0x1000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_MCK>;
clock-names = "apb_pclk";
in-ports {
@@ -63,7 +64,7 @@ etm@73c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x73c000 0x1000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_MCK>;
clock-names = "apb_pclk";
out-ports {
@@ -133,7 +134,7 @@ usb0: gadget@300000 {
reg = <0x00300000 0x100000
0xfc02c000 0x400>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE SAMA5D2_PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -151,7 +152,7 @@ usb2: usb@500000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00500000 0x100000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -176,7 +177,7 @@ ebi: ebi@10000000 {
0x1 0x0 0x60000000 0x10000000
0x2 0x0 0x70000000 0x10000000
0x3 0x0 0x80000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_MCK2>;
status = "disabled";
nand_controller: nand-controller {
@@ -195,7 +196,7 @@ sdmmc0: sdio-host@a0000000 {
compatible = "atmel,sama5d2-sdhci";
reg = <0xa0000000 0x300>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE SAMA5D2_PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
assigned-clock-rates = <480000000>;
@@ -206,7 +207,7 @@ sdmmc1: sdio-host@b0000000 {
compatible = "atmel,sama5d2-sdhci";
reg = <0xb0000000 0x300>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE SAMA5D2_PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
assigned-clock-rates = <480000000>;
@@ -696,7 +697,7 @@ pit: timer@f8048030 {
compatible = "atmel,at91sam9260-pit";
reg = <0xf8048030 0x10>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_MCK2>;
};
watchdog: watchdog@f8048040 {
@@ -734,7 +735,7 @@ AT91_XDMAC_DT_PERID(31))>,
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
clock-names = "pclk", "gclk";
- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
+ assigned-clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_I2S0_MUX>;
assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
status = "disabled";
};
@@ -749,7 +750,7 @@ can0: can@f8054000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_UTMI>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
@@ -1134,7 +1135,7 @@ AT91_XDMAC_DT_PERID(33))>,
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
clock-names = "pclk", "gclk";
- assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
+ assigned-clocks = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_I2S1_MUX>;
assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>;
status = "disabled";
};
@@ -1149,7 +1150,7 @@ can1: can@fc050000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA5D2_PMC_UTMI>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
status = "disabled";
diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi
index 00ba59ac1968c..a4e6ad652152c 100644
--- a/arch/arm/boot/dts/microchip/sama5d3.dtsi
+++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,sama5d3-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
@@ -1028,7 +1029,7 @@ pit: timer@fffffe30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D3_PMC_MCK>;
};
watchdog: watchdog@fffffe40 {
@@ -1071,7 +1072,7 @@ usb0: gadget@500000 {
reg = <0x00500000 0x100000
0xf8030000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE SAMA5D3_PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -1089,7 +1090,7 @@ usb2: usb@700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D3_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -1105,7 +1106,7 @@ ebi: ebi@10000000 {
0x1 0x0 0x40000000 0x10000000
0x2 0x0 0x50000000 0x10000000
0x3 0x0 0x60000000 0x10000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D3_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi
index ec1d68c640dea..d41377c465c4f 100644
--- a/arch/arm/boot/dts/microchip/sama5d4.dtsi
+++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/atmel,sama5d4-pmc.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/pinctrl/at91.h>
@@ -116,7 +117,7 @@ usb0: gadget@400000 {
reg = <0x00400000 0x100000
0xfc02c000 0x4000>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE SAMA5D4_PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -134,7 +135,7 @@ usb2: usb@600000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00600000 0x100000>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D4_PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -159,7 +160,7 @@ ebi: ebi@10000000 {
0x1 0x0 0x60000000 0x10000000
0x2 0x0 0x70000000 0x10000000
0x3 0x0 0x80000000 0x8000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D4_PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
@@ -753,7 +754,7 @@ pit: timer@fc068630 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfc068630 0x10>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA5D4_PMC_MCK2>;
};
watchdog: watchdog@fc068640 {
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index cd2cf9a6f40b8..246fc0e5fe21f 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -9,6 +9,7 @@
*/
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/microchip,sama7d65-pmc.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -30,7 +31,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
reg = <0x0>;
device_type = "cpu";
- clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_CPUPLL>;
clock-names = "cpu";
d-cache-size = <0x8000>; // L1, 32 KB
i-cache-size = <0x8000>; // L1, 32 KB
@@ -186,7 +187,7 @@ can0: can@e0828000 {
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
assigned-clock-rates = <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_UTMI>;
bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -202,7 +203,7 @@ can1: can@e082c000 {
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
assigned-clock-rates = <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_UTMI>;
bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -218,7 +219,7 @@ can2: can@e0830000 {
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
assigned-clock-rates = <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_UTMI>;
bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -234,7 +235,7 @@ can3: can@e0834000 {
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
assigned-clock-rates = <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_UTMI>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -250,7 +251,7 @@ can4: can@e0838000 {
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
assigned-clock-rates = <40000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_UTMI>;
bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
status = "disabled";
};
@@ -274,7 +275,7 @@ sdmmc1: mmc@e1208000 {
clock-names = "hclock", "multclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
assigned-clock-rates = <200000000>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7D65_PMC_MCK1>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi
index 03ef3d9aaeec6..b8296391fc696 100644
--- a/arch/arm/boot/dts/microchip/sama7g5.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/clock/microchip,sama7g5-pmc.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/at91-usart.h>
@@ -34,7 +35,7 @@ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
- clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_CPUPLL>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
@@ -202,7 +203,7 @@ ebi: ebi@40000000 {
0x1 0x0 0x48000000 0x8000000
0x2 0x0 0x50000000 0x8000000
0x3 0x0 0x58000000 0x8000000>;
- clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MCK1>;
status = "disabled";
nand_controller: nand-controller {
@@ -385,7 +386,7 @@ can0: can@e0828000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
status = "disabled";
@@ -401,7 +402,7 @@ can1: can@e082c000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
status = "disabled";
@@ -417,7 +418,7 @@ can2: can@e0830000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
status = "disabled";
@@ -433,7 +434,7 @@ can3: can@e0834000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
status = "disabled";
@@ -449,7 +450,7 @@ can4: can@e0838000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
status = "disabled";
@@ -465,7 +466,7 @@ can5: can@e083c000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
clock-names = "hclk", "cclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clock-rates = <40000000>;
bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
status = "disabled";
@@ -496,7 +497,7 @@ sdmmc0: mmc@e1204000 {
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
clock-names = "hclock", "multclk";
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
assigned-clock-rates = <200000000>;
microchip,sdcal-inverted;
@@ -509,7 +510,7 @@ sdmmc1: mmc@e1208000 {
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
clock-names = "hclock", "multclk";
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
assigned-clock-rates = <200000000>;
microchip,sdcal-inverted;
@@ -522,7 +523,7 @@ sdmmc2: mmc@e120c000 {
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
clock-names = "hclock", "multclk";
- assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_SYSPLL>;
assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
assigned-clock-rates = <200000000>;
microchip,sdcal-inverted;
--
2.47.3These clocks should be enabled, datasheet says:
> The OTPC is clocked through the Power Management Controller (PMC).
> The user must power on the main RC oscillator and enable the
> peripheral clock of the OTPC prior to reading or writing the OTP
> memory.
Earlier discussions suggest, MCK0 must be enabled, too. MCK0 is parent
of peripheral otpc_clk, so this is done implicitly.
Link: https://lore.kernel.org/linux-clk/ec34efc2-2051-4b8a-b5d8-6e2fd5e08c28@microchip.com/T/#u
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Removed clock-names, not part of bindings anymore, and not used by driver
v2:
- new patch, not present in v1
arch/arm/boot/dts/microchip/sama7g5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi
index b8296391fc696..30193f3bf9775 100644
--- a/arch/arm/boot/dts/microchip/sama7g5.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi
@@ -1036,6 +1036,7 @@ otpc: efuse@e8c00000 {
reg = <0xe8c00000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
+ clocks = <&pmc PMC_TYPE_CORE SAMA7G5_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 67>;
temperature_calib: calib@1 {
reg = <OTP_PKT(1) 76>;
--
2.47.3The One-Time Programmable (OTP) Memory Controller (OTPC) is the secure
interface between the system and the OTP memory. It also features the
Unique Product ID (UID) registers containing a unique serial number.
See datasheet (DS60001579G) sections "7. Memories" and "23. OTP Memory
Controller (OTPC)" for reference.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Removed needless header include
- Removed clock-names, not part of bindings anymore, and not used by driver
v2:
- squashed with patch adding the clock properties
arch/arm/boot/dts/microchip/sam9x60.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index f9e3962faca3f..098996739a62f 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -157,6 +157,14 @@ sdmmc1: sdio-host@90000000 {
status = "disabled";
};
+ otpc: efuse@eff00000 {
+ compatible = "microchip,sam9x60-otpc", "syscon";
+ reg = <0xeff00000 0xec>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 46>;
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
--
2.47.3Allows to access the OTP memory and Product UID now.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- Reworded commit message after reordering patches
v2:
- same as in v1, no changes
arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts
index b9ffd9e5faacc..c110a8e87568a 100644
--- a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts
+++ b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts
@@ -252,6 +252,10 @@ ethernet-phy@0 {
};
};
+&otpc {
+ status = "okay";
+};
+
&pinctrl {
adc {
pinctrl_adc_default: adc-default {
--
2.47.3Those were split up per SoC and are not used anymore.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
Notes:
v3:
- new patch, not present in v2
include/dt-bindings/clock/at91.h | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index f2a7b7d39c0d0..ebc41cb4edb92 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -14,38 +14,6 @@
#define PMC_TYPE_GCK 3
#define PMC_TYPE_PROGRAMMABLE 4
-#define PMC_SLOW 0
-#define PMC_MCK 1
-#define PMC_UTMI 2
-#define PMC_MAIN 3
-#define PMC_MCK2 4
-#define PMC_I2S0_MUX 5
-#define PMC_I2S1_MUX 6
-#define PMC_PLLACK 7
-#define PMC_PLLBCK 8
-#define PMC_AUDIOPLLCK 9
-#define PMC_AUDIOPINCK 10
-
-/* SAMA7G5 */
-#define PMC_CPUPLL (PMC_MAIN + 1)
-#define PMC_SYSPLL (PMC_MAIN + 2)
-#define PMC_DDRPLL (PMC_MAIN + 3)
-#define PMC_IMGPLL (PMC_MAIN + 4)
-#define PMC_BAUDPLL (PMC_MAIN + 5)
-#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
-#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
-#define PMC_ETHPLL (PMC_MAIN + 8)
-#define PMC_CPU (PMC_MAIN + 9)
-#define PMC_MCK1 (PMC_MAIN + 10)
-
-/* SAM9X7 */
-#define PMC_PLLADIV2 (PMC_MAIN + 11)
-#define PMC_LVDSPLL (PMC_MAIN + 12)
-
-/* SAMA7D65 */
-#define PMC_MCK3 (PMC_MAIN + 13)
-#define PMC_MCK5 (PMC_MAIN + 14)
-
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
#define AT91_PMC_LOCKA 1 /* PLLA Lock */
--
2.47.3On Tue, 20 Jan 2026 16:44:53 +0100, Alexander Dahl wrote: > Those were split up per SoC and are not used anymore. > > Signed-off-by: Alexander Dahl <ada@thorsis.com> > --- > > Notes: > v3: > - new patch, not present in v2 > > include/dt-bindings/clock/at91.h | 32 -------------------------------- > 1 file changed, 32 deletions(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
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