Add fsl,max-link-speed property for pcie_ep[0,1].

Fixes: 3b1d5deb29ff ("arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index a4d854817559..255cf942f87a 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1910,6 +1910,7 @@ pcie0_ep: pcie-ep@4c300000 {
 						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
 			msi-map = <0x0 &its 0x10 0x1>;
 			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+			fsl,max-link-speed = <3>;
 			status = "disabled";
 		};
 
@@ -1987,6 +1988,7 @@ pcie1_ep: pcie-ep@4c380000 {
 						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
 			msi-map = <0x0 &its 0x98 0x1>;
 			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+			fsl,max-link-speed = <3>;
 			status = "disabled";
 		};
 
-- 
2.37.1

On Tue, Jan 20, 2026 at 3:21 AM Richard Zhu <hongxing.zhu@nxp.com> wrote:
>
> Add fsl,max-link-speed property for pcie_ep[0,1].

Hi Richard,

Can you explain in the commit message why this change is needed?

What problem does it fix.

fsl,max-link-speed  is an optional property with a default of 1.

So it is perfectly fine to skip it as the initial patch does.

Thanks,
Daniel