Add CPUFreq support for the AM62L3 SoC with the appropriate
AM62L3 speed grade constants according to the datasheet [1].
This follows the same architecture-specific implementation pattern
as other TI SoCs in the AM6x family.
While at it, also sort instances where the SOC family names
were not sorted alphabetically.
[1] https://www.ti.com/lit/pdf/SPRSPA1
Signed-off-by: Dhruva Gole <d-gole@ti.com>
---
drivers/cpufreq/ti-cpufreq.c | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..3d1129aeed02b06f5877663a1b87521a230e3b32 100644
--- a/drivers/cpufreq/ti-cpufreq.c
+++ b/drivers/cpufreq/ti-cpufreq.c
@@ -70,6 +70,12 @@ enum {
#define AM62A7_SUPPORT_R_MPU_OPP BIT(1)
#define AM62A7_SUPPORT_V_MPU_OPP BIT(2)
+#define AM62L3_EFUSE_E_MPU_OPP 5
+#define AM62L3_EFUSE_O_MPU_OPP 15
+
+#define AM62L3_SUPPORT_E_MPU_OPP BIT(0)
+#define AM62L3_SUPPORT_O_MPU_OPP BIT(1)
+
#define AM62P5_EFUSE_O_MPU_OPP 15
#define AM62P5_EFUSE_S_MPU_OPP 19
#define AM62P5_EFUSE_T_MPU_OPP 20
@@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
return calculated_efuse;
}
+static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
+ unsigned long efuse)
+{
+ unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
+
+ switch (efuse) {
+ case AM62L3_EFUSE_O_MPU_OPP:
+ calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
+ fallthrough;
+ case AM62L3_EFUSE_E_MPU_OPP:
+ calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
+ }
+
+ return calculated_efuse;
+}
+
static struct ti_cpufreq_soc_data am3x_soc_data = {
.efuse_xlate = amx3_efuse_xlate,
.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
@@ -313,8 +335,9 @@ static struct ti_cpufreq_soc_data am3517_soc_data = {
static const struct soc_device_attribute k3_cpufreq_soc[] = {
{ .family = "AM62X", },
{ .family = "AM62AX", },
- { .family = "AM62PX", },
{ .family = "AM62DX", },
+ { .family = "AM62LX", },
+ { .family = "AM62PX", },
{ /* sentinel */ }
};
@@ -335,6 +358,14 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = {
.multi_regulator = false,
};
+static struct ti_cpufreq_soc_data am62l3_soc_data = {
+ .efuse_xlate = am62l3_efuse_xlate,
+ .efuse_offset = 0x0,
+ .efuse_mask = 0x07c0,
+ .efuse_shift = 0x6,
+ .multi_regulator = false,
+};
+
static struct ti_cpufreq_soc_data am62p5_soc_data = {
.efuse_xlate = am62p5_efuse_xlate,
.efuse_offset = 0x0,
@@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = {
{ .compatible = "ti,am625", .data = &am625_soc_data, },
{ .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
{ .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
+ { .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
{ .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
/* legacy */
{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
--
2.34.1
On 1/20/26 05:47, Dhruva Gole wrote:
> Add CPUFreq support for the AM62L3 SoC with the appropriate
> AM62L3 speed grade constants according to the datasheet [1].
>
> This follows the same architecture-specific implementation pattern
> as other TI SoCs in the AM6x family.
>
> While at it, also sort instances where the SOC family names
> were not sorted alphabetically.
>
> [1] https://www.ti.com/lit/pdf/SPRSPA1
>
> Signed-off-by: Dhruva Gole <d-gole@ti.com>
> ---
> drivers/cpufreq/ti-cpufreq.c | 34 +++++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..3d1129aeed02b06f5877663a1b87521a230e3b32 100644
> --- a/drivers/cpufreq/ti-cpufreq.c
> +++ b/drivers/cpufreq/ti-cpufreq.c
> @@ -70,6 +70,12 @@ enum {
> #define AM62A7_SUPPORT_R_MPU_OPP BIT(1)
> #define AM62A7_SUPPORT_V_MPU_OPP BIT(2)
>
> +#define AM62L3_EFUSE_E_MPU_OPP 5
> +#define AM62L3_EFUSE_O_MPU_OPP 15
> +
> +#define AM62L3_SUPPORT_E_MPU_OPP BIT(0)
> +#define AM62L3_SUPPORT_O_MPU_OPP BIT(1)
> +
> #define AM62P5_EFUSE_O_MPU_OPP 15
> #define AM62P5_EFUSE_S_MPU_OPP 19
> #define AM62P5_EFUSE_T_MPU_OPP 20
> @@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
> return calculated_efuse;
> }
>
> +static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
> + unsigned long efuse)
> +{
> + unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
> +
> + switch (efuse) {
> + case AM62L3_EFUSE_O_MPU_OPP:
> + calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
> + fallthrough;
> + case AM62L3_EFUSE_E_MPU_OPP:
> + calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
> + }
> +
> + return calculated_efuse;
> +}
> +
> static struct ti_cpufreq_soc_data am3x_soc_data = {
> .efuse_xlate = amx3_efuse_xlate,
> .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
> @@ -313,8 +335,9 @@ static struct ti_cpufreq_soc_data am3517_soc_data = {
> static const struct soc_device_attribute k3_cpufreq_soc[] = {
> { .family = "AM62X", },
> { .family = "AM62AX", },
> - { .family = "AM62PX", },
> { .family = "AM62DX", },
> + { .family = "AM62LX", },
> + { .family = "AM62PX", },
> { /* sentinel */ }
> };
>
> @@ -335,6 +358,14 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = {
> .multi_regulator = false,
> };
>
> +static struct ti_cpufreq_soc_data am62l3_soc_data = {
> + .efuse_xlate = am62l3_efuse_xlate,
> + .efuse_offset = 0x0,
> + .efuse_mask = 0x07c0,
> + .efuse_shift = 0x6,
> + .multi_regulator = false,
> +};
> +
> static struct ti_cpufreq_soc_data am62p5_soc_data = {
> .efuse_xlate = am62p5_efuse_xlate,
> .efuse_offset = 0x0,
> @@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[] __maybe_unused = {
> { .compatible = "ti,am625", .data = &am625_soc_data, },
> { .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
> { .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
> + { .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
> { .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
> /* legacy */
> { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
>
Hi Dhruva,
Reviewed-by: Kendall Willis <k-willis@ti.com>
Best,
Kendall Willis
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