From: Petr Hodina <phodina@protonmail.com>
The lanes must not be initialized before the driver has access to
the lane configuration, as it depends on whether D-PHY or C-PHY mode
is in use. Move the lane initialization to a later stage where the
configuration structures are available.
Signed-off-by: Petr Hodina <phodina@protonmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++--------
1 file changed, 57 insertions(+), 34 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index f3a8625511e1e..9e8470358515f 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1048,6 +1048,62 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
u8 val;
int i;
+ switch (csiphy->camss->res->version) {
+ case CAMSS_845:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sdm845[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
+ }
+ break;
+ case CAMSS_2290:
+ case CAMSS_6150:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_qcm2290[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+ }
+ break;
+ case CAMSS_7280:
+ case CAMSS_8250:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sm8250[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
+ }
+ break;
+ case CAMSS_8280XP:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sc8280xp[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
+ }
+ break;
+ case CAMSS_X1E80100:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_x1e80100[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
+ }
+ break;
+ case CAMSS_8550:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sm8550[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
+ }
+ break;
+ case CAMSS_8650:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sm8650[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+ }
+ break;
+ case CAMSS_8300:
+ case CAMSS_8775P:
+ { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sa8775p[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+ }
+ break;
+ default:
+ break;
+ }
+
settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
val = 0;
@@ -1119,49 +1175,16 @@ static int csiphy_init(struct csiphy_device *csiphy)
return -ENOMEM;
csiphy->regs = regs;
- regs->offset = 0x800;
regs->common_status_offset = 0xb0;
switch (csiphy->camss->res->version) {
- case CAMSS_845:
- regs->lane_regs = &lane_regs_sdm845[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
- break;
- case CAMSS_2290:
- case CAMSS_6150:
- regs->lane_regs = &lane_regs_qcm2290[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
- break;
- case CAMSS_7280:
- case CAMSS_8250:
- regs->lane_regs = &lane_regs_sm8250[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
- break;
- case CAMSS_8280XP:
- regs->lane_regs = &lane_regs_sc8280xp[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
- break;
case CAMSS_X1E80100:
- regs->lane_regs = &lane_regs_x1e80100[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
- regs->offset = 0x1000;
- break;
case CAMSS_8550:
- regs->lane_regs = &lane_regs_sm8550[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
- regs->offset = 0x1000;
- break;
case CAMSS_8650:
- regs->lane_regs = &lane_regs_sm8650[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
regs->offset = 0x1000;
break;
- case CAMSS_8300:
- case CAMSS_8775P:
- regs->lane_regs = &lane_regs_sa8775p[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
- break;
default:
+ regs->offset = 0x800;
break;
}
--
2.51.0
On 17/01/2026 15:36, David Heidelberg via B4 Relay wrote:
> From: Petr Hodina <phodina@protonmail.com>
>
> The lanes must not be initialized before the driver has access to
> the lane configuration, as it depends on whether D-PHY or C-PHY mode
> is in use. Move the lane initialization to a later stage where the
> configuration structures are available.
>
> Signed-off-by: Petr Hodina <phodina@protonmail.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++--------
> 1 file changed, 57 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index f3a8625511e1e..9e8470358515f 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -1048,6 +1048,62 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
> u8 val;
> int i;
>
> + switch (csiphy->camss->res->version) {
> + case CAMSS_845:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sdm845[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
> + }
> + break;
> + case CAMSS_2290:
> + case CAMSS_6150:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_qcm2290[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
> + }
> + break;
> + case CAMSS_7280:
> + case CAMSS_8250:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sm8250[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> + }
> + break;
> + case CAMSS_8280XP:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sc8280xp[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> + }
> + break;
> + case CAMSS_X1E80100:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_x1e80100[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
> + }
> + break;
> + case CAMSS_8550:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sm8550[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> + }
> + break;
> + case CAMSS_8650:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sm8650[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
> + }
> + break;
> + case CAMSS_8300:
> + case CAMSS_8775P:
> + { /* V4L2_MBUS_CSI2_DPHY */
> + regs->lane_regs = &lane_regs_sa8775p[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> + }
> + break;
> + default:
> + break;
> + }
> +
> settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>
> val = 0;
> @@ -1119,49 +1175,16 @@ static int csiphy_init(struct csiphy_device *csiphy)
> return -ENOMEM;
>
> csiphy->regs = regs;
> - regs->offset = 0x800;
> regs->common_status_offset = 0xb0;
>
> switch (csiphy->camss->res->version) {
> - case CAMSS_845:
> - regs->lane_regs = &lane_regs_sdm845[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
> - break;
> - case CAMSS_2290:
> - case CAMSS_6150:
> - regs->lane_regs = &lane_regs_qcm2290[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
> - break;
> - case CAMSS_7280:
> - case CAMSS_8250:
> - regs->lane_regs = &lane_regs_sm8250[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
> - break;
> - case CAMSS_8280XP:
> - regs->lane_regs = &lane_regs_sc8280xp[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
> - break;
> case CAMSS_X1E80100:
> - regs->lane_regs = &lane_regs_x1e80100[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
> - regs->offset = 0x1000;
> - break;
> case CAMSS_8550:
> - regs->lane_regs = &lane_regs_sm8550[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> - regs->offset = 0x1000;
> - break;
> case CAMSS_8650:
> - regs->lane_regs = &lane_regs_sm8650[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
> regs->offset = 0x1000;
> break;
> - case CAMSS_8300:
> - case CAMSS_8775P:
> - regs->lane_regs = &lane_regs_sa8775p[0];
> - regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> - break;
> default:
> + regs->offset = 0x800;
> break;
> }
>
>
Subject to testing.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
bod
On 17/01/2026 16:36, David Heidelberg via B4 Relay wrote: > From: Petr Hodina <phodina@protonmail.com> > > The lanes must not be initialized before the driver has access to > the lane configuration, as it depends on whether D-PHY or C-PHY mode > is in use. Move the lane initialization to a later stage where the > configuration structures are available. > > Signed-off-by: Petr Hodina <phodina@protonmail.com> > Signed-off-by: David Heidelberg <david@ixit.cz> > --- > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++-------- > 1 file changed, 57 insertions(+), 34 deletions(-) > Now we going to setup D/C-PHY in lanes_enable, which I perceive as sub-optimal, because when C-PHY is set on the device-tree level, while the device may handle both D-PHY and C-PHY, the intent is use C-PHY only when available, because of the advantages, where as disadvantages are mainly in the implementation complexity (which is already done). Thus it would be most optimal to take care of the configuration in the csiphy init, which starts at point, where the device-tree properties aren't parsed yet. I tried to do shuffling in camss_probe to make csiphy->cfg.csi2->lane_cfg available in the subdevice (csiphy) init phase. Everytime I moved camss_parse_ports earlier or camss_init_subdevices later I got into some kind of trouble, thus I assume current solution is (at least until some rewrite) best. David
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