perf/amd/ibs: Fixes + future enhancements

[PATCH 06/11] perf/amd/ibs: Add new MSRs and CPUID bits definitions

Posted by Ravi Bangoria 3 weeks, 3 days ago

IBS on upcoming microarch introduced two new control MSRs and couple of
new features. Define macros for them.

New capabilities:

 o IBS_CAPS_DIS: Alternate Fetch and Op IBS disable bits
 o IBS_CAPS_FETCHLAT: Fetch Latency filter
 o IBS_CAPS_BIT63_FILTER: Virtual address bit 63 based filters for Fetch
   and Op
 o IBS_CAPS_STRMST_RMTSOCKET: Streaming store filter and indicator,
   remote socket indicator

New control MSRs for above features:

 o MSR_AMD64_IBSFETCHCTL2
 o MSR_AMD64_IBSOPCTL2

Also do cosmetic alignment changes.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
---
 arch/x86/include/asm/msr-index.h  |  2 ++
 arch/x86/include/asm/perf_event.h | 52 ++++++++++++++++++++-----------
 2 files changed, 35 insertions(+), 19 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3d0a0950d20a..d8b3f3abe583 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -693,6 +693,8 @@
 #define MSR_AMD64_IBSBRTARGET		0xc001103b
 #define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
 #define MSR_AMD64_IBSOPDATA4		0xc001103d
+#define MSR_AMD64_IBSOPCTL2		0xc001103e
+#define MSR_AMD64_IBSFETCHCTL2		0xc001103f
 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
 #define MSR_AMD64_SVM_AVIC_DOORBELL	0xc001011b
 #define MSR_AMD64_VM_PAGE_FLUSH		0xc001011e
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 0d9af4135e0a..6f5ec5c9d5b4 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -639,6 +639,10 @@ struct arch_pebs_cntr_header {
 #define IBS_CAPS_OPDATA4		(1U<<10)
 #define IBS_CAPS_ZEN4			(1U<<11)
 #define IBS_CAPS_OPLDLAT		(1U<<12)
+#define IBS_CAPS_DIS			(1U<<13)
+#define IBS_CAPS_FETCHLAT		(1U<<14)
+#define IBS_CAPS_BIT63_FILTER		(1U<<15)
+#define IBS_CAPS_STRMST_RMTSOCKET	(1U<<16)
 #define IBS_CAPS_OPDTLBPGSIZE		(1U<<19)
 
 #define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
@@ -653,31 +657,41 @@ struct arch_pebs_cntr_header {
 #define IBSCTL_LVT_OFFSET_MASK		0x0F
 
 /* IBS fetch bits/masks */
-#define IBS_FETCH_L3MISSONLY	(1ULL<<59)
-#define IBS_FETCH_RAND_EN	(1ULL<<57)
-#define IBS_FETCH_VAL		(1ULL<<49)
-#define IBS_FETCH_ENABLE	(1ULL<<48)
-#define IBS_FETCH_CNT		0xFFFF0000ULL
-#define IBS_FETCH_MAX_CNT	0x0000FFFFULL
+#define IBS_FETCH_L3MISSONLY		      (1ULL << 59)
+#define IBS_FETCH_RAND_EN		      (1ULL << 57)
+#define IBS_FETCH_VAL			      (1ULL << 49)
+#define IBS_FETCH_ENABLE		      (1ULL << 48)
+#define IBS_FETCH_CNT			     0xFFFF0000ULL
+#define IBS_FETCH_MAX_CNT		     0x0000FFFFULL
+
+#define IBS_FETCH_2_DIS			      (1ULL <<  0)
+#define IBS_FETCH_2_FETCH_LAT_FILTER	    (0xFULL <<  1)
+#define IBS_FETCH_2_EXCL_RIP_63_EQ_1	      (1ULL <<  5)
+#define IBS_FETCH_2_EXCL_RIP_63_EQ_0	      (1ULL <<  6)
 
 /*
  * IBS op bits/masks
  * The lower 7 bits of the current count are random bits
  * preloaded by hardware and ignored in software
  */
-#define IBS_OP_LDLAT_EN		(1ULL<<63)
-#define IBS_OP_LDLAT_THRSH	(0xFULL<<59)
-#define IBS_OP_CUR_CNT		(0xFFF80ULL<<32)
-#define IBS_OP_CUR_CNT_RAND	(0x0007FULL<<32)
-#define IBS_OP_CUR_CNT_EXT_MASK	(0x7FULL<<52)
-#define IBS_OP_CNT_CTL		(1ULL<<19)
-#define IBS_OP_VAL		(1ULL<<18)
-#define IBS_OP_ENABLE		(1ULL<<17)
-#define IBS_OP_L3MISSONLY	(1ULL<<16)
-#define IBS_OP_MAX_CNT		0x0000FFFFULL
-#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
-#define IBS_OP_MAX_CNT_EXT_MASK	(0x7FULL<<20)	/* separate upper 7 bits */
-#define IBS_RIP_INVALID		(1ULL<<38)
+#define IBS_OP_LDLAT_EN			      (1ULL << 63)
+#define IBS_OP_LDLAT_THRSH		    (0xFULL << 59)
+#define IBS_OP_CUR_CNT			(0xFFF80ULL << 32)
+#define IBS_OP_CUR_CNT_RAND		(0x0007FULL << 32)
+#define IBS_OP_CUR_CNT_EXT_MASK		   (0x7FULL << 52)
+#define IBS_OP_CNT_CTL			      (1ULL << 19)
+#define IBS_OP_VAL			      (1ULL << 18)
+#define IBS_OP_ENABLE			      (1ULL << 17)
+#define IBS_OP_L3MISSONLY		      (1ULL << 16)
+#define IBS_OP_MAX_CNT			     0x0000FFFFULL
+#define IBS_OP_MAX_CNT_EXT		     0x007FFFFFULL	/* not a register bit mask */
+#define IBS_OP_MAX_CNT_EXT_MASK		   (0x7FULL << 20)	/* separate upper 7 bits */
+#define IBS_RIP_INVALID			      (1ULL << 38)
+
+#define IBS_OP_2_DIS			      (1ULL <<  0)
+#define IBS_OP_2_EXCL_RIP_63_EQ_0	      (1ULL <<  1)
+#define IBS_OP_2_EXCL_RIP_63_EQ_1	      (1ULL <<  2)
+#define IBS_OP_2_STRM_ST_FILTER		      (1ULL <<  3)
 
 #ifdef CONFIG_X86_LOCAL_APIC
 extern u32 get_ibs_caps(void);
-- 
2.43.0

Re: [PATCH 06/11] perf/amd/ibs: Add new MSRs and CPUID bits definitions

Posted by Mi, Dapeng 2 weeks, 6 days ago

On 1/16/2026 11:34 AM, Ravi Bangoria wrote:
> IBS on upcoming microarch introduced two new control MSRs and couple of
> new features. Define macros for them.
>
> New capabilities:
>
>  o IBS_CAPS_DIS: Alternate Fetch and Op IBS disable bits
>  o IBS_CAPS_FETCHLAT: Fetch Latency filter
>  o IBS_CAPS_BIT63_FILTER: Virtual address bit 63 based filters for Fetch
>    and Op
>  o IBS_CAPS_STRMST_RMTSOCKET: Streaming store filter and indicator,
>    remote socket indicator
>
> New control MSRs for above features:
>
>  o MSR_AMD64_IBSFETCHCTL2
>  o MSR_AMD64_IBSOPCTL2
>
> Also do cosmetic alignment changes.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
> ---
>  arch/x86/include/asm/msr-index.h  |  2 ++
>  arch/x86/include/asm/perf_event.h | 52 ++++++++++++++++++++-----------
>  2 files changed, 35 insertions(+), 19 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 3d0a0950d20a..d8b3f3abe583 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -693,6 +693,8 @@
>  #define MSR_AMD64_IBSBRTARGET		0xc001103b
>  #define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
>  #define MSR_AMD64_IBSOPDATA4		0xc001103d
> +#define MSR_AMD64_IBSOPCTL2		0xc001103e
> +#define MSR_AMD64_IBSFETCHCTL2		0xc001103f
>  #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
>  #define MSR_AMD64_SVM_AVIC_DOORBELL	0xc001011b
>  #define MSR_AMD64_VM_PAGE_FLUSH		0xc001011e
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 0d9af4135e0a..6f5ec5c9d5b4 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -639,6 +639,10 @@ struct arch_pebs_cntr_header {
>  #define IBS_CAPS_OPDATA4		(1U<<10)
>  #define IBS_CAPS_ZEN4			(1U<<11)
>  #define IBS_CAPS_OPLDLAT		(1U<<12)
> +#define IBS_CAPS_DIS			(1U<<13)
> +#define IBS_CAPS_FETCHLAT		(1U<<14)
> +#define IBS_CAPS_BIT63_FILTER		(1U<<15)
> +#define IBS_CAPS_STRMST_RMTSOCKET	(1U<<16)
>  #define IBS_CAPS_OPDTLBPGSIZE		(1U<<19)
>  
>  #define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
> @@ -653,31 +657,41 @@ struct arch_pebs_cntr_header {
>  #define IBSCTL_LVT_OFFSET_MASK		0x0F
>  
>  /* IBS fetch bits/masks */
> -#define IBS_FETCH_L3MISSONLY	(1ULL<<59)
> -#define IBS_FETCH_RAND_EN	(1ULL<<57)
> -#define IBS_FETCH_VAL		(1ULL<<49)
> -#define IBS_FETCH_ENABLE	(1ULL<<48)
> -#define IBS_FETCH_CNT		0xFFFF0000ULL
> -#define IBS_FETCH_MAX_CNT	0x0000FFFFULL
> +#define IBS_FETCH_L3MISSONLY		      (1ULL << 59)
> +#define IBS_FETCH_RAND_EN		      (1ULL << 57)
> +#define IBS_FETCH_VAL			      (1ULL << 49)
> +#define IBS_FETCH_ENABLE		      (1ULL << 48)
> +#define IBS_FETCH_CNT			     0xFFFF0000ULL
> +#define IBS_FETCH_MAX_CNT		     0x0000FFFFULL
> +
> +#define IBS_FETCH_2_DIS			      (1ULL <<  0)
> +#define IBS_FETCH_2_FETCH_LAT_FILTER	    (0xFULL <<  1)
> +#define IBS_FETCH_2_EXCL_RIP_63_EQ_1	      (1ULL <<  5)
> +#define IBS_FETCH_2_EXCL_RIP_63_EQ_0	      (1ULL <<  6)
>  
>  /*
>   * IBS op bits/masks
>   * The lower 7 bits of the current count are random bits
>   * preloaded by hardware and ignored in software
>   */
> -#define IBS_OP_LDLAT_EN		(1ULL<<63)
> -#define IBS_OP_LDLAT_THRSH	(0xFULL<<59)
> -#define IBS_OP_CUR_CNT		(0xFFF80ULL<<32)
> -#define IBS_OP_CUR_CNT_RAND	(0x0007FULL<<32)
> -#define IBS_OP_CUR_CNT_EXT_MASK	(0x7FULL<<52)
> -#define IBS_OP_CNT_CTL		(1ULL<<19)
> -#define IBS_OP_VAL		(1ULL<<18)
> -#define IBS_OP_ENABLE		(1ULL<<17)
> -#define IBS_OP_L3MISSONLY	(1ULL<<16)
> -#define IBS_OP_MAX_CNT		0x0000FFFFULL
> -#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
> -#define IBS_OP_MAX_CNT_EXT_MASK	(0x7FULL<<20)	/* separate upper 7 bits */
> -#define IBS_RIP_INVALID		(1ULL<<38)
> +#define IBS_OP_LDLAT_EN			      (1ULL << 63)
> +#define IBS_OP_LDLAT_THRSH		    (0xFULL << 59)
> +#define IBS_OP_CUR_CNT			(0xFFF80ULL << 32)
> +#define IBS_OP_CUR_CNT_RAND		(0x0007FULL << 32)
> +#define IBS_OP_CUR_CNT_EXT_MASK		   (0x7FULL << 52)
> +#define IBS_OP_CNT_CTL			      (1ULL << 19)
> +#define IBS_OP_VAL			      (1ULL << 18)
> +#define IBS_OP_ENABLE			      (1ULL << 17)
> +#define IBS_OP_L3MISSONLY		      (1ULL << 16)
> +#define IBS_OP_MAX_CNT			     0x0000FFFFULL
> +#define IBS_OP_MAX_CNT_EXT		     0x007FFFFFULL	/* not a register bit mask */
> +#define IBS_OP_MAX_CNT_EXT_MASK		   (0x7FULL << 20)	/* separate upper 7 bits */
> +#define IBS_RIP_INVALID			      (1ULL << 38)
> +
> +#define IBS_OP_2_DIS			      (1ULL <<  0)
> +#define IBS_OP_2_EXCL_RIP_63_EQ_0	      (1ULL <<  1)
> +#define IBS_OP_2_EXCL_RIP_63_EQ_1	      (1ULL <<  2)
> +#define IBS_OP_2_STRM_ST_FILTER		      (1ULL <<  3)
>  
>  #ifdef CONFIG_X86_LOCAL_APIC
>  extern u32 get_ibs_caps(void);

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>